pokecrystal/home/init.asm

215 lines
2.7 KiB
NASM
Raw Normal View History

2018-06-24 14:09:41 +00:00
Reset::
2013-08-20 07:26:37 +00:00
di
call InitSound
2013-08-20 07:26:37 +00:00
xor a
ldh [hMapAnims], a
2013-08-20 07:26:37 +00:00
call ClearPalettes
xor a
ldh [rIF], a
2019-05-05 16:14:46 +00:00
ld a, 1 << VBLANK
ldh [rIE], a
2013-08-20 07:26:37 +00:00
ei
2015-02-10 23:14:41 +00:00
ld hl, wcfbe
2013-08-20 07:26:37 +00:00
set 7, [hl]
ld c, 32
call DelayFrames
jr Init
2018-06-24 14:09:41 +00:00
_Start::
2013-08-20 07:26:37 +00:00
cp $11
jr z, .cgb
2013-08-20 07:26:37 +00:00
xor a
jr .load
2013-08-20 07:26:37 +00:00
.cgb
2013-08-20 07:26:37 +00:00
ld a, $1
.load
ldh [hCGB], a
2013-08-20 07:26:37 +00:00
ld a, $1
ldh [hSystemBooted], a
2013-08-20 07:26:37 +00:00
2018-06-24 14:09:41 +00:00
Init::
2013-08-20 07:26:37 +00:00
di
xor a
ldh [rIF], a
ldh [rIE], a
ldh [rRP], a
ldh [rSCX], a
ldh [rSCY], a
ldh [rSB], a
ldh [rSC], a
ldh [rWX], a
ldh [rWY], a
ldh [rBGP], a
ldh [rOBP0], a
ldh [rOBP1], a
ldh [rTMA], a
ldh [rTAC], a
ld [WRAM1_Begin], a
2013-08-20 07:26:37 +00:00
ld a, %100 ; Start timer at 4096Hz
ldh [rTAC], a
2013-08-20 07:26:37 +00:00
.wait
ldh a, [rLY]
2017-12-29 17:53:21 +00:00
cp LY_VBLANK + 1
2013-08-20 07:26:37 +00:00
jr nz, .wait
xor a
ldh [rLCDC], a
2013-08-20 07:26:37 +00:00
; Clear WRAM bank 0
ld hl, WRAM0_Begin
ld bc, WRAM0_End - WRAM0_Begin
.ByteFill:
2013-08-20 07:26:37 +00:00
ld [hl], 0
inc hl
dec bc
ld a, b
or c
jr nz, .ByteFill
2013-08-20 07:26:37 +00:00
2018-01-23 21:49:58 +00:00
ld sp, wStack
2013-08-20 07:26:37 +00:00
; Clear HRAM
ldh a, [hCGB]
2013-08-20 07:26:37 +00:00
push af
ldh a, [hSystemBooted]
2013-08-20 07:26:37 +00:00
push af
xor a
ld hl, HRAM_Begin
ld bc, HRAM_End - HRAM_Begin
2013-08-20 07:26:37 +00:00
call ByteFill
pop af
ldh [hSystemBooted], a
2013-08-20 07:26:37 +00:00
pop af
ldh [hCGB], a
2013-08-20 07:26:37 +00:00
call ClearWRAM
2018-01-18 06:25:19 +00:00
ld a, 1
ldh [rSVBK], a
2013-08-20 07:26:37 +00:00
call ClearVRAM
call ClearSprites
call ClearsScratch
2013-08-20 07:26:37 +00:00
ld a, BANK(GameInit) ; aka BANK(WriteOAMDMACodeToHRAM)
2013-08-20 07:26:37 +00:00
rst Bankswitch
2018-01-30 19:47:14 +00:00
call WriteOAMDMACodeToHRAM
2013-08-20 07:26:37 +00:00
xor a
ldh [hMapAnims], a
ldh [hSCX], a
ldh [hSCY], a
ldh [rJOYP], a
2013-08-20 07:26:37 +00:00
ld a, $8 ; HBlank int enable
ldh [rSTAT], a
2013-08-20 07:26:37 +00:00
ld a, $90
ldh [hWY], a
ldh [rWY], a
2013-08-20 07:26:37 +00:00
ld a, 7
ldh [hWX], a
ldh [rWX], a
2013-08-20 07:26:37 +00:00
2017-12-29 18:22:33 +00:00
ld a, LCDC_DEFAULT ; %11100011
2013-08-20 07:26:37 +00:00
; LCD on
; Win tilemap 1
; Win on
; BG/Win tiledata 0
; BG Tilemap 0
; OBJ 8x8
; OBJ on
; BG on
ldh [rLCDC], a
2013-08-20 07:26:37 +00:00
ld a, CONNECTION_NOT_ESTABLISHED
ldh [hSerialConnectionStatus], a
2013-08-20 07:26:37 +00:00
2017-12-24 17:47:30 +00:00
farcall InitCGBPals
2013-08-20 07:26:37 +00:00
2017-12-28 12:32:33 +00:00
ld a, HIGH(vBGMap1)
ldh [hBGMapAddress + 1], a
2017-12-28 12:32:33 +00:00
xor a ; LOW(vBGMap1)
ldh [hBGMapAddress], a
2013-08-20 07:26:37 +00:00
2017-12-24 17:47:30 +00:00
farcall StartClock
2013-08-20 07:26:37 +00:00
xor a
ld [MBC3LatchClock], a
ld [MBC3SRamEnable], a
ldh a, [hCGB]
2013-08-20 07:26:37 +00:00
and a
2016-05-05 19:07:37 +00:00
jr z, .no_double_speed
2013-09-08 07:12:48 +00:00
call NormalSpeed
2016-05-05 19:07:37 +00:00
.no_double_speed
2013-08-20 07:26:37 +00:00
xor a
ldh [rIF], a
2019-05-05 16:14:46 +00:00
ld a, IE_DEFAULT
ldh [rIE], a
2013-08-20 07:26:37 +00:00
ei
call DelayFrame
predef InitSGBBorder ; SGB init
2013-08-20 07:26:37 +00:00
call InitSound
2013-08-20 07:26:37 +00:00
xor a
2014-05-21 20:21:46 +00:00
ld [wMapMusic], a
2013-08-20 07:26:37 +00:00
jp GameInit
2018-06-24 14:09:41 +00:00
ClearVRAM::
2013-08-20 07:26:37 +00:00
; Wipe VRAM banks 0 and 1
ld a, 1
ldh [rVBK], a
2013-08-20 07:26:37 +00:00
call .clear
2018-01-18 06:25:19 +00:00
xor a ; 0
ldh [rVBK], a
2013-08-20 07:26:37 +00:00
.clear
2018-01-18 06:25:19 +00:00
ld hl, VRAM_Begin
ld bc, VRAM_End - VRAM_Begin
2013-08-20 07:26:37 +00:00
xor a
call ByteFill
ret
2018-06-24 14:09:41 +00:00
ClearWRAM::
2013-08-20 07:26:37 +00:00
; Wipe swappable WRAM banks (1-7)
; Assumes CGB or AGB
2013-08-20 07:26:37 +00:00
ld a, 1
.bank_loop
2013-08-20 07:26:37 +00:00
push af
ldh [rSVBK], a
2013-08-20 07:26:37 +00:00
xor a
ld hl, WRAM1_Begin
ld bc, WRAM1_End - WRAM1_Begin
2013-08-20 07:26:37 +00:00
call ByteFill
pop af
inc a
cp 8
2016-05-19 12:11:44 +00:00
jr nc, .bank_loop ; Should be jr c
2013-08-20 07:26:37 +00:00
ret
2018-06-24 14:09:41 +00:00
ClearsScratch::
; Wipe the first 32 bytes of sScratch
ld a, BANK(sScratch)
2013-08-20 07:26:37 +00:00
call GetSRAMBank
ld hl, sScratch
ld bc, $20
2013-08-20 07:26:37 +00:00
xor a
call ByteFill
call CloseSRAM
ret