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1582 Commits

Author SHA1 Message Date
0xd4d d8ed3c82bf
Update codecov.yml 2020-11-15 23:50:18 +01:00
0xd4d 079f93e52d C#9 2020-11-15 19:59:27 +01:00
0xd4d 49fd258ee1 Use is not null 2020-11-11 02:21:25 +01:00
0xd4d 0abcec127c Change netcoreapp3.1 -> net5.0 2020-11-11 00:04:50 +01:00
0xd4d d2d84afc59 Add GMI instructions 2020-11-11 00:04:41 +01:00
0xd4d b6ad2638c2 Update PCOMMIT: may vm exit, not in enclave, may abort tsx 2020-11-09 22:10:25 +01:00
0xd4d 07cce4ef98 Add tests 2020-11-09 13:31:36 +01:00
0xd4d 1dae747648 Use Cyrix decoder option when decoding 2 3DNow! instructions and change them to 16/32-bit only 2020-11-09 13:17:38 +01:00
0xd4d a351396936 Add --release to some lines, fix a warning 2020-11-09 02:48:55 +01:00
0xd4d 9938e31434 Update README 2020-11-09 02:48:47 +01:00
0xd4d 5fd4bf33e5 Update build files 2020-11-07 13:25:29 +01:00
0xd4d aade59ec81 Update build files to support dash, zsh 2020-11-07 12:21:34 +01:00
0xd4d 037aede1b0 Update build.yml 2020-11-07 01:06:39 +01:00
0xd4d 0f681ad50f Move build code to build scripts in build dir 2020-11-07 01:04:09 +01:00
0xd4d b5da1bd6c6 blk enc: use xbegin rel16 if possible, else use rel32 2020-11-05 18:39:13 +01:00
0xd4d 74833ab768 Change imm2 to imm4 (upper 2 bits are ignored by the CPU) 2020-11-04 18:34:58 +01:00
0xd4d 803ede15f9 ENCODEKEY{128,256}: Clear flags, only a possible future extension may set flags 2020-11-04 18:34:49 +01:00
0xd4d 34fd2aac0c Use zmmword ptr 2020-11-04 18:34:42 +01:00
0xd4d 8c78d4de73 Add reg32 to intel fmt tpause/umwait 2020-11-04 18:34:34 +01:00
0xd4d 2ebf72a156 Trim lines 2020-11-04 18:34:23 +01:00
0xd4d e8b346c307 Update implied-reg & const imm parser code 2020-10-31 16:51:00 +01:00
0xd4d 1264536c34 Clean up switch 2020-10-31 16:50:51 +01:00
0xd4d 5f388f5545 Remove modrm prefix 2020-10-31 16:50:44 +01:00
0xd4d e79a13c84c Remove unused code 2020-10-31 16:50:36 +01:00
0xd4d 7bb371db1a Remove cflow=tsx 2020-10-31 13:24:03 +01:00
0xd4d d7ae045cff Move more lines to flags line 2020-10-31 13:23:55 +01:00
0xd4d 5956636b42 Simplify ops line in defs.txt 2020-10-31 00:24:39 +01:00
0xd4d 0fe4530024 Change the props to return size in bits instead of size in bytes 2020-10-31 00:24:30 +01:00
0xd4d 97aa0cdcdd Use switch expr, reformat 2020-10-31 00:24:17 +01:00
0xd4d 28ebc9b967 Use regdef.Name instead of enum.ToString() 2020-10-31 00:24:09 +01:00
0xd4d 8a287d29a0 Add opkind defs 2020-10-29 21:44:25 +01:00
0xd4d be58b9fd73 Add mnemonic/memsz/bcstmemsz props 2020-10-29 21:41:45 +01:00
0xd4d d83f4e25bb Move branch/cc lines to flags line 2020-10-29 21:41:36 +01:00
0xd4d 1a4ed51a03 Update docs 2020-10-29 21:41:25 +01:00
0xd4d dee5a101eb Update rflags (vmlaunch,vmresume,vmptrst) 2020-10-28 01:27:36 +01:00
0xd4d ca841eb9d1 saverestore -> save-restore 2020-10-28 01:27:26 +01:00
0xd4d 0f25011858
Merge pull request #126 from 0xd4d/rel191 
Bump version
 2020-10-27 20:14:51 +01:00
0xd4d f1edb8a35a Bump version 2020-10-27 19:34:39 +01:00
0xd4d 3ed6e0eadf Update build.yml 2020-10-26 19:49:09 +01:00
0xd4d e32b6ba516 Generate sp-inc switch code 2020-10-25 21:14:37 +01:00
0xd4d c0a73435bb Add a doc example 2020-10-25 21:14:30 +01:00
0xd4d 6709d3cb1d Add FPU condition code bits and Instruction.GetFpuStackIncrementInfo() 2020-10-25 17:53:14 +01:00
0xd4d 07346b7ea6 Remove save-restore from some instrs and add accessed reg ranges 2020-10-24 11:27:16 +02:00
0xd4d 18bf2fb655 Rename flag 2020-10-24 11:27:07 +02:00
0xd4d 21eee4c7be Remove #[cfg] 2020-10-22 18:38:11 +02:00
0xd4d 6154dc84ef Test without an index (tileloadd{,t1},tilestored) 2020-10-22 18:17:36 +02:00
0xd4d 51dd9984cf Ignore stride index when calculating the VA (`TILELOADD{,T1}`, `TILESTORED`) 2020-10-22 17:53:11 +02:00
0xd4d 6bc3a87dfe Add tile-stride-index 2020-10-22 17:29:44 +02:00
0xd4d b3f730cd04 Don't show ignored segment by default, closes #111 2020-10-22 17:29:31 +02:00
0xd4d 976f2cb192 Add prefetch flag 2020-10-22 17:29:17 +02:00