Rooba
/
iced
mirror of https://github.com/icedland/iced.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add GMI instructions

This commit is contained in:
0xd4d 2020-11-11 00:04:41 +01:00
parent b6ad2638c2
commit d2d84afc59
102 changed files with 1404 additions and 158 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/UnitTests/Intel/Decoder/Code.32Only.txt
View File

@ -253,3 +253,5 @@ Cyrix_DEDC
Cyrix_DEDD
Cyrix_DEDE
Frinear
Ccs_hash_16
Ccs_encrypt_16

2
src/UnitTests/Intel/Decoder/Code.64Only.txt
View File

@ -466,3 +466,5 @@ Testui
Clui
Stui
Senduipi_r64
Ccs_hash_64
Ccs_encrypt_64

20
src/UnitTests/Intel/Decoder/DecoderTest16.txt
View File

@ -21772,3 +21772,23 @@ C4C249 53 10, VEX_Vpdpwssds_xmm_xmm_xmmm128, Vpdpwssds, 3, op0=r;xmm2 op1=r;xmm6
C4E24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=m;ds;bx;si;1;0;0;Packed256_Int16
C4E24D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=r;ymm3
C4C24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=m;ds;bx;si;1;0;0;Packed256_Int16 enc=C4E24D5310
F3 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep
F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16
F2 F3 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep enc=F30FA6E8
F3 F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16
0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16
F3 67 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8
67 F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep
67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32
F3 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep
F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16
F2 F3 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=F30FA7F0
F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16
0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16
F3 67 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0
67 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep
67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32

20
src/UnitTests/Intel/Decoder/DecoderTest32.txt
View File

@ -21773,3 +21773,23 @@ C4C249 53 10, VEX_Vpdpwssds_xmm_xmm_xmmm128, Vpdpwssds, 3, op0=r;xmm2 op1=r;xmm6
C4E24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=m;ds;eax;;1;0;0;Packed256_Int16
C4E24D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=r;ymm3
C4C24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=m;ds;eax;;1;0;0;Packed256_Int16 enc=C4E24D5310
F3 67 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep enc=67F30FA6E8
67 F3 0FA6 E8, Ccs_hash_16, Ccs_hash, 0, rep
67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_16
F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep
F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32
F2 F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=F30FA6E8
F3 F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32
0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32
F3 67 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep enc=67F30FA7F0
67 F3 0FA7 F0, Ccs_encrypt_16, Ccs_encrypt, 0, rep
67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_16
F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep
F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32
F2 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=F30FA7F0
F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32
0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32

32
src/UnitTests/Intel/Decoder/DecoderTest64.txt
View File

@ -32531,3 +32531,35 @@ C4624D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm10 op1=r;ymm
C4E20D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm14 op2=r;ymm3
C4C24D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=r;ymm11
C4A24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, 3, op0=r;ymm2 op1=r;ymm6 op2=m;ds;rax;;1;0;0;Packed256_Int16 enc=C4E24D5310
F3 67 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8
67 F3 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep
67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32
67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 decopt=Xbts no_opt_disable_test
67 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_32 decopt=Cmpxchg486A no_opt_disable_test
67 F3 4F 0FA6 E8, Ccs_hash_32, Ccs_hash, 0, rep enc=67F30FA6E8
F3 0FA6 E8, Ccs_hash_64, Ccs_hash, 0, rep
F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64
F2 F3 0FA6 E8, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8
F3 F2 0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64
0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64
0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64 decopt=Xbts no_opt_disable_test
0FA6 E8, INVALID, INVALID, 0, code=Ccs_hash_64 decopt=Cmpxchg486A no_opt_disable_test
F3 4F 0FA6 E8, Ccs_hash_64, Ccs_hash, 0, rep enc=F30FA6E8
F3 67 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0
67 F3 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep
67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32
67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 decopt=Xbts no_opt_disable_test
67 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_32 decopt=Cmpxchg486A no_opt_disable_test
67 F3 4F 0FA7 F0, Ccs_encrypt_32, Ccs_encrypt, 0, rep enc=67F30FA7F0
F3 0FA7 F0, Ccs_encrypt_64, Ccs_encrypt, 0, rep
F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64
F2 F3 0FA7 F0, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0
F3 F2 0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64
0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64
0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 decopt=Xbts no_opt_disable_test
0FA7 F0, INVALID, INVALID, 0, code=Ccs_encrypt_64 decopt=Cmpxchg486A no_opt_disable_test
F3 4F 0FA7 F0, Ccs_encrypt_64, Ccs_encrypt, 0, rep enc=F30FA7F0

6
src/UnitTests/Intel/Encoder/OpCodeInfos.txt
View File

@ -4335,3 +4335,9 @@ VEX_Vpdpwssd_xmm_xmm_xmmm128, Vpdpwssd, Packed128_Int16, Unknown, VEX, 66, 0F38,
VEX_Vpdpwssd_ymm_ymm_ymmm256, Vpdpwssd, Packed256_Int16, Unknown, VEX, 66, 0F38, 52, VEX.256.66.0F38.W0 52 /r, VPDPWSSD ymm1| ymm2| ymm3/m256, 16 32 64 cpl0 cpl1 cpl2 cpl3 L256 W0 op=ymm_reg;ymm_vvvv;ymm_or_mem intel16 intel32 intel64 amd16 amd32 amd64 pm cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
VEX_Vpdpwssds_xmm_xmm_xmmm128, Vpdpwssds, Packed128_Int16, Unknown, VEX, 66, 0F38, 53, VEX.128.66.0F38.W0 53 /r, VPDPWSSDS xmm1| xmm2| xmm3/m128, 16 32 64 cpl0 cpl1 cpl2 cpl3 L128 W0 op=xmm_reg;xmm_vvvv;xmm_or_mem intel16 intel32 intel64 amd16 amd32 amd64 pm cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
VEX_Vpdpwssds_ymm_ymm_ymmm256, Vpdpwssds, Packed256_Int16, Unknown, VEX, 66, 0F38, 53, VEX.256.66.0F38.W0 53 /r, VPDPWSSDS ymm1| ymm2| ymm3/m256, 16 32 64 cpl0 cpl1 cpl2 cpl3 L256 W0 op=ymm_reg;ymm_vvvv;ymm_or_mem intel16 intel32 intel64 amd16 amd32 amd64 pm cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
Ccs_hash_16, Ccs_hash, Unknown, Unknown, legacy, F3, 0F, A6E8, a16 F3 0F A6 E8, CCS_HASH, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
Ccs_hash_32, Ccs_hash, Unknown, Unknown, legacy, F3, 0F, A6E8, a32 F3 0F A6 E8, CCS_HASH, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
Ccs_hash_64, Ccs_hash, Unknown, Unknown, legacy, F3, 0F, A6E8, a64 F3 0F A6 E8, CCS_HASH, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
Ccs_encrypt_16, Ccs_encrypt, Unknown, Unknown, legacy, F3, 0F, A7F0, a16 F3 0F A7 F0, CCS_ENCRYPT, 16 32 cpl0 cpl1 cpl2 cpl3 a16 intel16 intel32 amd16 amd32 rm pm v86 cm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
Ccs_encrypt_32, Ccs_encrypt, Unknown, Unknown, legacy, F3, 0F, A7F0, a32 F3 0F A7 F0, CCS_ENCRYPT, 16 32 64 cpl0 cpl1 cpl2 cpl3 a32 intel16 intel32 intel64 amd16 amd32 amd64 rm pm v86 cm lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam
Ccs_encrypt_64, Ccs_encrypt, Unknown, Unknown, legacy, F3, 0F, A7F0, a64 F3 0F A7 F0, CCS_ENCRYPT, 64 cpl0 cpl1 cpl2 cpl3 a64 intel64 amd64 lm outside-smm in-smm outside-sgx in-sgx1 in-sgx2 outside-vmx-op in-vmx-root-op in-vmx-non-root-op outside-seam in-seam

4
src/UnitTests/Intel/Formatter/Fast/Test32_Default.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1,mm5
pfrcpv mm1,[eax-5AA5EDCCh]
pfrsqrtv mm1,mm5
pfrsqrtv mm1,[eax-5AA5EDCCh]
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Fast/Test32_Inverted.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, qword ptr ds:[eax-0x5aa5edcc]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, qword ptr ds:[eax-0x5aa5edcc]
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Fast/Test64_Default.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2,xmm6,[rax]
vpdpwssds xmm2,xmm6,xmm3
vpdpwssds ymm2,ymm6,[rax]
vpdpwssds ymm2,ymm6,ymm3
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Fast/Test64_Inverted.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, xmmword ptr ds:[rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, ymmword ptr ds:[rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Gas/Test32_ForceSuffix.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm5, mm1
pfrcpv -0x5aa5edcc(eax), mm1
pfrsqrtv mm5, mm1
pfrsqrtv -0x5aa5edcc(eax), mm1
rep ccs_hash
addr16 rep ccs_hash
rep ccs_encrypt
addr16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Gas/Test32_NoSuffix.txt
View File

@ -745,3 +745,7 @@ pfrcpv %mm5,%mm1
pfrcpv -0x5aa5edcc(%eax),%mm1
pfrsqrtv %mm5,%mm1
pfrsqrtv -0x5aa5edcc(%eax),%mm1
rep ccs_hash
addr16 rep ccs_hash
rep ccs_encrypt
addr16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Gas/Test64_ForceSuffix.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds (rax), xmm6, xmm2
vpdpwssds xmm3, xmm6, xmm2
vpdpwssds (rax), ymm6, ymm2
vpdpwssds ymm3, ymm6, ymm2
rep ccs_hash
addr32 rep ccs_hash
rep ccs_encrypt
addr32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Gas/Test64_NoSuffix.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds (%rax),%xmm6,%xmm2
vpdpwssds %xmm3,%xmm6,%xmm2
vpdpwssds (%rax),%ymm6,%ymm2
vpdpwssds %ymm3,%ymm6,%ymm2
rep ccs_hash
addr32 rep ccs_hash
rep ccs_encrypt
addr32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/InstructionInfos32.txt
View File

@ -745,3 +745,7 @@ DF FC, Frinear, Cyrix
0F0F 88 34125AA5 86, D3NOW_Pfrcpv_mm_mmm64, Cyrix
0F0F CD 87, D3NOW_Pfrsqrtv_mm_mmm64, Cyrix
0F0F 88 34125AA5 87, D3NOW_Pfrsqrtv_mm_mmm64, Cyrix
F3 0FA6 E8, Ccs_hash_32
67 F3 0FA6 E8, Ccs_hash_16
F3 0FA7 F0, Ccs_encrypt_32
67 F3 0FA7 F0, Ccs_encrypt_16

4
src/UnitTests/Intel/Formatter/InstructionInfos64.txt
View File

@ -8402,3 +8402,7 @@ C4E249 53 10, VEX_Vpdpwssds_xmm_xmm_xmmm128
C4E249 53 D3, VEX_Vpdpwssds_xmm_xmm_xmmm128
C4E24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256
C4E24D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256
F3 0FA6 E8, Ccs_hash_64
67 F3 0FA6 E8, Ccs_hash_32
F3 0FA7 F0, Ccs_encrypt_64
67 F3 0FA7 F0, Ccs_encrypt_32

4
src/UnitTests/Intel/Formatter/Intel/Test32_MemAlways.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, qword ptr [eax-0x5aa5edcc]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, qword ptr [eax-0x5aa5edcc]
rep ccs_hash
addr16 rep ccs_hash
rep ccs_encrypt
addr16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Intel/Test32_MemDefault.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1,mm5
pfrcpv mm1,[eax-0x5aa5edcc]
pfrsqrtv mm1,mm5
pfrsqrtv mm1,[eax-0x5aa5edcc]
rep ccs_hash
addr16 rep ccs_hash
rep ccs_encrypt
addr16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Intel/Test32_MemMinimum.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, [eax-0x5aa5edcc]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, [eax-0x5aa5edcc]
rep ccs_hash
addr16 rep ccs_hash
rep ccs_encrypt
addr16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Intel/Test64_MemAlways.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, xmmword ptr [rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, ymmword ptr [rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
addr32 rep ccs_hash
rep ccs_encrypt
addr32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Intel/Test64_MemDefault.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2,xmm6,[rax]
vpdpwssds xmm2,xmm6,xmm3
vpdpwssds ymm2,ymm6,[rax]
vpdpwssds ymm2,ymm6,ymm3
rep ccs_hash
addr32 rep ccs_hash
rep ccs_encrypt
addr32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Intel/Test64_MemMinimum.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, [rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, [rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
addr32 rep ccs_hash
rep ccs_encrypt
addr32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Masm/Test32_MemAlways.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, mmword ptr [eax-5AA5EDCCh]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, mmword ptr [eax-5AA5EDCCh]
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Masm/Test32_MemDefault.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1,mm5
pfrcpv mm1,[eax-5AA5EDCCh]
pfrsqrtv mm1,mm5
pfrsqrtv mm1,[eax-5AA5EDCCh]
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Masm/Test32_MemMinimum.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, [eax-5AA5EDCCh]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, [eax-5AA5EDCCh]
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Masm/Test64_MemAlways.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, xmmword ptr [rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, ymmword ptr [rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Masm/Test64_MemDefault.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2,xmm6,[rax]
vpdpwssds xmm2,xmm6,xmm3
vpdpwssds ymm2,ymm6,[rax]
vpdpwssds ymm2,ymm6,ymm3
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Masm/Test64_MemMinimum.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, [rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, [rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
rep ccs_hash
rep ccs_encrypt
rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Nasm/Test32_MemAlways.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, qword [eax-0x5aa5edcc]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, qword [eax-0x5aa5edcc]
rep ccs_hash
a16 rep ccs_hash
rep ccs_encrypt
a16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Nasm/Test32_MemDefault.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1,mm5
pfrcpv mm1,[eax-0x5aa5edcc]
pfrsqrtv mm1,mm5
pfrsqrtv mm1,[eax-0x5aa5edcc]
rep ccs_hash
a16 rep ccs_hash
rep ccs_encrypt
a16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Nasm/Test32_MemMinimum.txt
View File

@ -745,3 +745,7 @@ pfrcpv mm1, mm5
pfrcpv mm1, [eax-0x5aa5edcc]
pfrsqrtv mm1, mm5
pfrsqrtv mm1, [eax-0x5aa5edcc]
rep ccs_hash
a16 rep ccs_hash
rep ccs_encrypt
a16 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Nasm/Test64_MemAlways.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, oword [rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, yword [rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
a32 rep ccs_hash
rep ccs_encrypt
a32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Nasm/Test64_MemDefault.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2,xmm6,[rax]
vpdpwssds xmm2,xmm6,xmm3
vpdpwssds ymm2,ymm6,[rax]
vpdpwssds ymm2,ymm6,ymm3
rep ccs_hash
a32 rep ccs_hash
rep ccs_encrypt
a32 rep ccs_encrypt

4
src/UnitTests/Intel/Formatter/Nasm/Test64_MemMinimum.txt
View File

@ -8402,3 +8402,7 @@ vpdpwssds xmm2, xmm6, [rax]
vpdpwssds xmm2, xmm6, xmm3
vpdpwssds ymm2, ymm6, [rax]
vpdpwssds ymm2, ymm6, ymm3
rep ccs_hash
a32 rep ccs_hash
rep ccs_encrypt
a32 rep ccs_encrypt

40
src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_16.txt
View File

@ -616,41 +616,41 @@ F3 0FA6 C0, Montmul_16, Legacy, PADLOCK_PMM, crm=es:si;Unknown cr=es;si cw=edx r
# rep montmul
67 F3 0FA6 C0, Montmul_32, Legacy, PADLOCK_PMM, crm=es:esi;Unknown cr=es;esi cw=edx r=ecx cr=eax cw=eax;ecx
# rep xsha1
F3 0FA6 C8, Xsha1_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si;di cr=ax cw=ax r=cx cw=cx
F3 0FA6 C8, Xsha1_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=ax;cx
# rep xsha1
67 F3 0FA6 C8, Xsha1_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi;edi cr=eax cw=eax r=ecx cw=ecx
67 F3 0FA6 C8, Xsha1_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=eax;ecx
# rep xsha256
F3 0FA6 D0, Xsha256_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si;di cr=ax cw=ax r=cx cw=cx
F3 0FA6 D0, Xsha256_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=ax;cx
# rep xsha256
67 F3 0FA6 D0, Xsha256_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi;edi cr=eax cw=eax r=ecx cw=ecx
67 F3 0FA6 D0, Xsha256_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=eax;ecx
# rep xstore
F3 0FA7 C0, Xstore_16, Legacy, PADLOCK_RNG, cwm=es:di;Unknown cr=es cr=di cw=di cr=edx cw=eax r=cx cw=cx
F3 0FA7 C0, Xstore_16, Legacy, PADLOCK_RNG, cwm=es:di;Unknown cr=es cr=di cw=di cr=edx cw=eax rcw=cx
# rep xstore
67 F3 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=es cr=edi cw=edi cr=edx cw=eax r=ecx cw=ecx
67 F3 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=es cr=edi cw=edi cr=edx cw=eax rcw=ecx
# xstore
0FA7 C0, Xstore_16, Legacy, PADLOCK_RNG, wm=es:di;Unknown r=es rw=di r=edx w=eax
# xstore
67 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, wm=es:edi;Unknown r=es rw=edi r=edx w=eax
# rep xcryptecb
F3 0FA7 C8, Xcryptecb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;dx;bx;si;di cw=si;di r=cx cw=cx
F3 0FA7 C8, Xcryptecb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptecb
67 F3 0FA7 C8, Xcryptecb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;edx;ebx;esi;edi cw=esi;edi r=ecx cw=ecx
67 F3 0FA7 C8, Xcryptecb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptcbc
F3 0FA7 D0, Xcryptcbc_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
F3 0FA7 D0, Xcryptcbc_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptcbc
67 F3 0FA7 D0, Xcryptcbc_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
67 F3 0FA7 D0, Xcryptcbc_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptctr
F3 0FA7 D8, Xcryptctr_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
F3 0FA7 D8, Xcryptctr_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptctr
67 F3 0FA7 D8, Xcryptctr_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
67 F3 0FA7 D8, Xcryptctr_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptcfb
F3 0FA7 E0, Xcryptcfb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
F3 0FA7 E0, Xcryptcfb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptcfb
67 F3 0FA7 E0, Xcryptcfb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
67 F3 0FA7 E0, Xcryptcfb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptofb
F3 0FA7 E8, Xcryptofb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
F3 0FA7 E8, Xcryptofb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptofb
67 F3 0FA7 E8, Xcryptofb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
67 F3 0FA7 E8, Xcryptofb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# maskmovq mm2,mm3
0FF7 D3, Maskmovq_rDI_mm_mm, Legacy, SSE, op0=w op1=r op2=r r=ds;di r=mm2 r=mm3 wm=ds:di;UInt64
# maskmovq mm2,mm3
@ -705,3 +705,11 @@ C7 F8 5AA5, Xbegin_rel16, Legacy, RTM, flow=XbeginXabortXend op0=r cw=eax
0F3C, Cpu_write, Legacy, CYRIX_DDI, priv r=eax;ebx decopt=Cyrix
# cpu_read
0F3D, Cpu_read, Legacy, CYRIX_DDI, priv r=ebx w=eax decopt=Cyrix
# rep ccs_hash
F3 0FA6 E8, Ccs_hash_16, Legacy, PADLOCK_GMI, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=ax;cx cr=bx
# rep ccs_hash
67 F3 0FA6 E8, Ccs_hash_32, Legacy, PADLOCK_GMI, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=eax;ecx cr=ebx
# rep ccs_encrypt
F3 0FA7 F0, Ccs_encrypt_16, Legacy, PADLOCK_GMI, crm=es:bx;Unknown crm=es:si;Unknown cwm=es:di;Unknown cr=es cr=bx;si;di cw=si;di rcw=cx cr=ax
# rep ccs_encrypt
67 F3 0FA7 F0, Ccs_encrypt_32, Legacy, PADLOCK_GMI, crm=es:ebx;Unknown crm=es:esi;Unknown cwm=es:edi;Unknown cr=es cr=ebx;esi;edi cw=esi;edi rcw=ecx cr=eax

40
src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_32.txt
View File

@ -1658,41 +1658,41 @@ C5ED FB CA, VEX_Vpsubq_ymm_ymm_ymmm256, VEX, AVX2, op0=w op1=n op2=n w=vmm1
# rep montmul
F3 0FA6 C0, Montmul_32, Legacy, PADLOCK_PMM, crm=es:esi;Unknown cr=es;esi cw=edx r=ecx cr=eax cw=eax;ecx
# rep xsha1
67 F3 0FA6 C8, Xsha1_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si;di cr=ax cw=ax r=cx cw=cx
67 F3 0FA6 C8, Xsha1_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=ax;cx
# rep xsha1
F3 0FA6 C8, Xsha1_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi;edi cr=eax cw=eax r=ecx cw=ecx
F3 0FA6 C8, Xsha1_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=eax;ecx
# rep xsha256
67 F3 0FA6 D0, Xsha256_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si;di cr=ax cw=ax r=cx cw=cx
67 F3 0FA6 D0, Xsha256_16, Legacy, PADLOCK_PHE, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=ax;cx
# rep xsha256
F3 0FA6 D0, Xsha256_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi;edi cr=eax cw=eax r=ecx cw=ecx
F3 0FA6 D0, Xsha256_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=eax;ecx
# rep xstore
67 F3 0FA7 C0, Xstore_16, Legacy, PADLOCK_RNG, cwm=es:di;Unknown cr=es cr=di cw=di cr=edx cw=eax r=cx cw=cx
67 F3 0FA7 C0, Xstore_16, Legacy, PADLOCK_RNG, cwm=es:di;Unknown cr=es cr=di cw=di cr=edx cw=eax rcw=cx
# rep xstore
F3 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=es cr=edi cw=edi cr=edx cw=eax r=ecx cw=ecx
F3 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=es cr=edi cw=edi cr=edx cw=eax rcw=ecx
# xstore
67 0FA7 C0, Xstore_16, Legacy, PADLOCK_RNG, wm=es:di;Unknown r=es rw=di r=edx w=eax
# xstore
0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, wm=es:edi;Unknown r=es rw=edi r=edx w=eax
# rep xcryptecb
67 F3 0FA7 C8, Xcryptecb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;dx;bx;si;di cw=si;di r=cx cw=cx
67 F3 0FA7 C8, Xcryptecb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptecb
F3 0FA7 C8, Xcryptecb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;edx;ebx;esi;edi cw=esi;edi r=ecx cw=ecx
F3 0FA7 C8, Xcryptecb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptcbc
67 F3 0FA7 D0, Xcryptcbc_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
67 F3 0FA7 D0, Xcryptcbc_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptcbc
F3 0FA7 D0, Xcryptcbc_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
F3 0FA7 D0, Xcryptcbc_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptctr
67 F3 0FA7 D8, Xcryptctr_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
67 F3 0FA7 D8, Xcryptctr_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptctr
F3 0FA7 D8, Xcryptctr_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
F3 0FA7 D8, Xcryptctr_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptcfb
67 F3 0FA7 E0, Xcryptcfb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
67 F3 0FA7 E0, Xcryptcfb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptcfb
F3 0FA7 E0, Xcryptcfb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
F3 0FA7 E0, Xcryptcfb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# rep xcryptofb
67 F3 0FA7 E8, Xcryptofb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=ax;si;di r=cx cw=cx
67 F3 0FA7 E8, Xcryptofb_16, Legacy, PADLOCK_ACE, cwm=es:di;Unknown crm=es:ax;Unknown cwm=es:ax;Unknown crm=es:dx;Unknown crm=es:bx;Unknown crm=es:si;Unknown cr=es;ax;dx;bx;si;di cw=si;di rcw=cx
# rep xcryptofb
F3 0FA7 E8, Xcryptofb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=eax;esi;edi r=ecx cw=ecx
F3 0FA7 E8, Xcryptofb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=es;eax;edx;ebx;esi;edi cw=esi;edi rcw=ecx
# maskmovq mm2,mm3
0FF7 D3, Maskmovq_rDI_mm_mm, Legacy, SSE, op0=w op1=r op2=r r=ds;edi r=mm2 r=mm3 wm=ds:edi;UInt64
# maskmovq mm2,mm3
@ -1985,3 +1985,11 @@ DF FC, Frinear, Legacy, CYRIX_FPU, fw=1 fu=023 rw=st0 decopt=Cyrix
0F0F CD 87, D3NOW_Pfrsqrtv_mm_mmm64, D3NOW, CYRIX_D3NOW, op0=w op1=r w=mm1 r=mm5 decopt=Cyrix
# pfrsqrtv mm1,[eax-5AA5EDCCh]
0F0F 88 34125AA5 87, D3NOW_Pfrsqrtv_mm_mmm64, D3NOW, CYRIX_D3NOW, op0=w op1=r w=mm1 r=ds;eax rm=ds:eax+0xFFFFFFFFA55A1234;Packed64_Float32 decopt=Cyrix
# rep ccs_hash
67 F3 0FA6 E8, Ccs_hash_16, Legacy, PADLOCK_GMI, crm=es:di;Unknown cwm=es:di;Unknown crm=es:si;Unknown cr=es cr=si;di cw=si rcw=ax;cx cr=bx
# rep ccs_hash
F3 0FA6 E8, Ccs_hash_32, Legacy, PADLOCK_GMI, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=es cr=esi;edi cw=esi rcw=eax;ecx cr=ebx
# rep ccs_encrypt
67 F3 0FA7 F0, Ccs_encrypt_16, Legacy, PADLOCK_GMI, crm=es:bx;Unknown crm=es:si;Unknown cwm=es:di;Unknown cr=es cr=bx;si;di cw=si;di rcw=cx cr=ax
# rep ccs_encrypt
F3 0FA7 F0, Ccs_encrypt_32, Legacy, PADLOCK_GMI, crm=es:ebx;Unknown crm=es:esi;Unknown cwm=es:edi;Unknown cr=es cr=ebx;esi;edi cw=esi;edi rcw=ecx cr=eax

38
src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
View File

@ -19072,15 +19072,15 @@ F3 0FA6 C0, Montmul_64, Legacy, PADLOCK_PMM, crm=es:rsi;Unknown cr=rsi cw=rdx r=
# rep montmul
67 F3 0FA6 C0, Montmul_32, Legacy, PADLOCK_PMM, crm=es:esi;Unknown cr=esi cw=rdx r=ecx cr=eax cw=rax;rcx
# rep xsha1
F3 0FA6 C8, Xsha1_64, Legacy, PADLOCK_PHE, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi;rdi cr=rax cw=rax r=rcx cw=rcx
F3 0FA6 C8, Xsha1_64, Legacy, PADLOCK_PHE, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi rcw=rax;rcx
# rep xsha1
67 F3 0FA6 C8, Xsha1_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi;rdi cr=eax cw=rax r=ecx cw=rcx
67 F3 0FA6 C8, Xsha1_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi r=eax;ecx cw=rax;rcx
# rep xsha256
F3 0FA6 D0, Xsha256_64, Legacy, PADLOCK_PHE, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi;rdi cr=rax cw=rax r=rcx cw=rcx
F3 0FA6 D0, Xsha256_64, Legacy, PADLOCK_PHE, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi rcw=rax;rcx
# rep xsha256
67 F3 0FA6 D0, Xsha256_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi;rdi cr=eax cw=rax r=ecx cw=rcx
67 F3 0FA6 D0, Xsha256_32, Legacy, PADLOCK_PHE, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi r=eax;ecx cw=rax;rcx
# rep xstore
F3 0FA7 C0, Xstore_64, Legacy, PADLOCK_RNG, cwm=es:rdi;Unknown cr=rdi cw=rdi cr=edx cw=rax r=rcx cw=rcx
F3 0FA7 C0, Xstore_64, Legacy, PADLOCK_RNG, cwm=es:rdi;Unknown cr=rdi cw=rdi cr=edx cw=rax rcw=rcx
# rep xstore
67 F3 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, cwm=es:edi;Unknown cr=edi cw=rdi cr=edx cw=rax r=ecx cw=rcx
# xstore
@ -19088,25 +19088,25 @@ F3 0FA7 C0, Xstore_64, Legacy, PADLOCK_RNG, cwm=es:rdi;Unknown cr=rdi cw=rdi cr=
# xstore
67 0FA7 C0, Xstore_32, Legacy, PADLOCK_RNG, wm=es:edi;Unknown r=edi w=rdi r=edx w=rax
# rep xcryptecb
F3 0FA7 C8, Xcryptecb_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rdx;rbx;rsi;rdi cw=rsi;rdi r=rcx cw=rcx
# rep xcryptecbs
F3 0FA7 C8, Xcryptecb_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rdx;rbx;rsi;rdi cw=rsi;rdi rcw=rcx
# rep xcryptecb
67 F3 0FA7 C8, Xcryptecb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=edx;ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx
# rep xcryptcbc
F3 0FA7 D0, Xcryptcbc_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rax;rsi;rdi r=rcx cw=rcx
F3 0FA7 D0, Xcryptcbc_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rsi;rdi rcw=rcx
# rep xcryptcbc
67 F3 0FA7 D0, Xcryptcbc_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rax;rsi;rdi r=ecx cw=rcx
67 F3 0FA7 D0, Xcryptcbc_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx
# rep xcryptctr
F3 0FA7 D8, Xcryptctr_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rax;rsi;rdi r=rcx cw=rcx
F3 0FA7 D8, Xcryptctr_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rsi;rdi rcw=rcx
# rep xcryptctr
67 F3 0FA7 D8, Xcryptctr_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rax;rsi;rdi r=ecx cw=rcx
67 F3 0FA7 D8, Xcryptctr_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx
# rep xcryptcfb
F3 0FA7 E0, Xcryptcfb_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rax;rsi;rdi r=rcx cw=rcx
F3 0FA7 E0, Xcryptcfb_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rsi;rdi rcw=rcx
# rep xcryptcfb
67 F3 0FA7 E0, Xcryptcfb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rax;rsi;rdi r=ecx cw=rcx
67 F3 0FA7 E0, Xcryptcfb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx
# rep xcryptofb
F3 0FA7 E8, Xcryptofb_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rax;rsi;rdi r=rcx cw=rcx
F3 0FA7 E8, Xcryptofb_64, Legacy, PADLOCK_ACE, cwm=es:rdi;Unknown crm=es:rax;Unknown cwm=es:rax;Unknown crm=es:rdx;Unknown crm=es:rbx;Unknown crm=es:rsi;Unknown cr=rax;rdx;rbx;rsi;rdi cw=rsi;rdi rcw=rcx
# rep xcryptofb
67 F3 0FA7 E8, Xcryptofb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rax;rsi;rdi r=ecx cw=rcx
67 F3 0FA7 E8, Xcryptofb_32, Legacy, PADLOCK_ACE, cwm=es:edi;Unknown crm=es:eax;Unknown cwm=es:eax;Unknown crm=es:edx;Unknown crm=es:ebx;Unknown crm=es:esi;Unknown cr=eax;edx;ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx
# db 66h
66, DeclareByte, Legacy, INTEL8086, flow=Exception special
# dw 4466h
@ -19257,3 +19257,11 @@ C4E249 53 10, VEX_Vpdpwssds_xmm_xmm_xmmm128, VEX, AVX_VNNI, op0=rw op1=r op2=r r
C4E24D 53 D3, VEX_Vpdpwssds_ymm_ymm_ymmm256, VEX, AVX_VNNI, op0=rw op1=r op2=r r=ymm2 w=vmm2 r=ymm6 r=ymm3
# vpdpwssds ymm2,ymm6,[rax]
C4E24D 53 10, VEX_Vpdpwssds_ymm_ymm_ymmm256, VEX, AVX_VNNI, op0=rw op1=r op2=r r=ymm2 w=vmm2 r=ymm6 r=rax rm=ds:rax;Packed256_Int16
# rep ccs_hash
F3 0FA6 E8, Ccs_hash_64, Legacy, PADLOCK_GMI, crm=es:rdi;Unknown cwm=es:rdi;Unknown crm=es:rsi;Unknown cr=rsi;rdi cw=rsi rcw=rax;rcx cr=rbx
# rep ccs_hash
67 F3 0FA6 E8, Ccs_hash_32, Legacy, PADLOCK_GMI, crm=es:edi;Unknown cwm=es:edi;Unknown crm=es:esi;Unknown cr=esi;edi cw=rsi r=eax;ecx cw=rax;rcx cr=ebx
# rep ccs_encrypt
67 F3 0FA7 F0, Ccs_encrypt_32, Legacy, PADLOCK_GMI, crm=es:ebx;Unknown crm=es:esi;Unknown cwm=es:edi;Unknown cr=ebx;esi;edi cw=rsi;rdi r=ecx cw=rcx cr=eax
# rep ccs_encrypt
F3 0FA7 F0, Ccs_encrypt_64, Legacy, PADLOCK_GMI, crm=es:rbx;Unknown crm=es:rsi;Unknown cwm=es:rdi;Unknown cr=rbx;rsi;rdi cw=rsi;rdi rcw=rcx cr=rax

16
src/csharp/Intel/Generator/Decoder/DecoderTable_Legacy.cs
View File

@ -1381,7 +1381,13 @@ namespace Generator.Decoder {
null,
// E8
null,
new object[] { legacyEnum[nameof(OpCodeHandlerKind.MandatoryPrefix4)],
invalid_NoModRM,
invalid_NoModRM,
new object[] { legacyEnum[nameof(OpCodeHandlerKind.Simple5)], codeEnum[nameof(Code.Ccs_hash_16)], codeEnum[nameof(Code.Ccs_hash_32)], codeEnum[nameof(Code.Ccs_hash_64)] },
invalid_NoModRM,
0x00,
},
null,
null,
null,
@ -1516,7 +1522,13 @@ namespace Generator.Decoder {
null,
// F0
null,
new object[] { legacyEnum[nameof(OpCodeHandlerKind.MandatoryPrefix4)],
invalid_NoModRM,
invalid_NoModRM,
new object[] { legacyEnum[nameof(OpCodeHandlerKind.Simple5)], codeEnum[nameof(Code.Ccs_encrypt_16)], codeEnum[nameof(Code.Ccs_encrypt_32)], codeEnum[nameof(Code.Ccs_encrypt_64)] },
invalid_NoModRM,
0x00,
},
null,
null,
null,

6
src/csharp/Intel/Generator/Enums/Code.cs
View File

@ -4343,6 +4343,12 @@ namespace Generator.Enums {
VEX_Vpdpwssd_ymm_ymm_ymmm256,
VEX_Vpdpwssds_xmm_xmm_xmmm128,
VEX_Vpdpwssds_ymm_ymm_ymmm256,
Ccs_hash_16,
Ccs_hash_32,
Ccs_hash_64,
Ccs_encrypt_16,
Ccs_encrypt_32,
Ccs_encrypt_64,
}
[TypeGen(TypeGenOrders.CreatedInstructions)]

2
src/csharp/Intel/Generator/Enums/InstructionInfo/CpuidFeature.cs
View File

@ -334,5 +334,7 @@ namespace Generator.Enums.InstructionInfo {
HRESET,
[Comment("CPUID.(EAX=07H, ECX=01H):EAX.AVX-VNNI[bit 4]")]
AVX_VNNI,
[Comment("CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.GMI[Bits 5:4] = 11B ([4] = exists, [5] = enabled)")]
PADLOCK_GMI,
}
}

2
src/csharp/Intel/Generator/Enums/Mnemonic.cs
View File

@ -1651,5 +1651,7 @@ namespace Generator.Enums {
Stui,
Senduipi,
Hreset,
Ccs_hash,
Ccs_encrypt,
}
}

1
src/csharp/Intel/Generator/Program.cs
View File

@ -257,6 +257,7 @@ Options:
options.ExcludeCpuid.Add(nameof(CpuidFeature.PADLOCK_PHE));
options.ExcludeCpuid.Add(nameof(CpuidFeature.PADLOCK_PMM));
options.ExcludeCpuid.Add(nameof(CpuidFeature.PADLOCK_RNG));
options.ExcludeCpuid.Add(nameof(CpuidFeature.PADLOCK_GMI));
break;
case "--no-cyrix":

110
src/csharp/Intel/Generator/Tables/InstructionDefs.txt
View File

@ -15859,7 +15859,7 @@ END
# Code: Xsha1_16
INSTRUCTION: a16 F3 0F A6 C8 | XSHA1 | PADLOCK_PHE
implied: cr=[es:si=Unknown] crcw=[es:di=Unknown] cw=si;di crcw=ax rcw=cx
implied: cr=[es:si=Unknown] crcw=[es:di=Unknown] cw=si rcw=ax;cx
code-suffix: 16
flags: 16 32
gas: asz
@ -15869,7 +15869,7 @@ END
# Code: Xsha1_32
INSTRUCTION: a32 F3 0F A6 C8 | XSHA1 | PADLOCK_PHE
implied: cr=[es:esi=Unknown] crcw=[es:edi=Unknown] cw=esi;edi crcw=eax rcw=ecx
implied: cr=[es:esi=Unknown] crcw=[es:edi=Unknown] cw=esi rcw=eax;ecx
code-suffix: 32
gas: asz
intel: asz
@ -15878,7 +15878,7 @@ END
# Code: Xsha1_64
INSTRUCTION: a64 F3 0F A6 C8 | XSHA1 | PADLOCK_PHE
implied: cr=[es:rsi=Unknown] crcw=[es:rdi=Unknown] cw=rsi;rdi crcw=rax rcw=rcx
implied: cr=[es:rsi=Unknown] crcw=[es:rdi=Unknown] cw=rsi rcw=rax;rcx
code-suffix: 64
flags: 64
gas: asz
@ -15888,7 +15888,7 @@ END
# Code: Xsha256_16
INSTRUCTION: a16 F3 0F A6 D0 | XSHA256 | PADLOCK_PHE
implied: cr=[es:si=Unknown] crcw=[es:di=Unknown] cw=si;di crcw=ax rcw=cx
implied: cr=[es:si=Unknown] crcw=[es:di=Unknown] cw=si rcw=ax;cx
code-suffix: 16
flags: 16 32
gas: asz
@ -15898,7 +15898,7 @@ END
# Code: Xsha256_32
INSTRUCTION: a32 F3 0F A6 D0 | XSHA256 | PADLOCK_PHE
implied: cr=[es:esi=Unknown] crcw=[es:edi=Unknown] cw=esi;edi crcw=eax rcw=ecx
implied: cr=[es:esi=Unknown] crcw=[es:edi=Unknown] cw=esi rcw=eax;ecx
code-suffix: 32
gas: asz
intel: asz
@ -15907,7 +15907,7 @@ END
# Code: Xsha256_64
INSTRUCTION: a64 F3 0F A6 D0 | XSHA256 | PADLOCK_PHE
implied: cr=[es:rsi=Unknown] crcw=[es:rdi=Unknown] cw=rsi;rdi crcw=rax rcw=rcx
implied: cr=[es:rsi=Unknown] crcw=[es:rdi=Unknown] cw=rsi rcw=rax;rcx
code-suffix: 64
flags: 64
gas: asz
@ -15992,7 +15992,7 @@ END
# Code: Xcryptcbc_16
INSTRUCTION: a16 F3 0F A7 D0 | XCRYPTCBC | PADLOCK_ACE
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=ax;si;di
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=si;di
code-suffix: 16
flags: 16 32
gas: asz
@ -16002,7 +16002,7 @@ END
# Code: Xcryptcbc_32
INSTRUCTION: a32 F3 0F A7 D0 | XCRYPTCBC | PADLOCK_ACE
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=eax;esi;edi
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=esi;edi
code-suffix: 32
gas: asz
intel: asz
@ -16011,7 +16011,7 @@ END
# Code: Xcryptcbc_64
INSTRUCTION: a64 F3 0F A7 D0 | XCRYPTCBC | PADLOCK_ACE
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rax;rsi;rdi
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rsi;rdi
code-suffix: 64
flags: 64
gas: asz
@ -16021,7 +16021,7 @@ END
# Code: Xcryptctr_16
INSTRUCTION: a16 F3 0F A7 D8 | XCRYPTCTR | PADLOCK_ACE
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=ax;si;di
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=si;di
code-suffix: 16
flags: 16 32
gas: asz
@ -16031,7 +16031,7 @@ END
# Code: Xcryptctr_32
INSTRUCTION: a32 F3 0F A7 D8 | XCRYPTCTR | PADLOCK_ACE
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=eax;esi;edi
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=esi;edi
code-suffix: 32
gas: asz
intel: asz
@ -16040,7 +16040,7 @@ END
# Code: Xcryptctr_64
INSTRUCTION: a64 F3 0F A7 D8 | XCRYPTCTR | PADLOCK_ACE
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rax;rsi;rdi
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rsi;rdi
code-suffix: 64
flags: 64
gas: asz
@ -16050,7 +16050,7 @@ END
# Code: Xcryptcfb_16
INSTRUCTION: a16 F3 0F A7 E0 | XCRYPTCFB | PADLOCK_ACE
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=ax;si;di
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=si;di
code-suffix: 16
flags: 16 32
gas: asz
@ -16060,7 +16060,7 @@ END
# Code: Xcryptcfb_32
INSTRUCTION: a32 F3 0F A7 E0 | XCRYPTCFB | PADLOCK_ACE
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=eax;esi;edi
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=esi;edi
code-suffix: 32
gas: asz
intel: asz
@ -16069,7 +16069,7 @@ END
# Code: Xcryptcfb_64
INSTRUCTION: a64 F3 0F A7 E0 | XCRYPTCFB | PADLOCK_ACE
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rax;rsi;rdi
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rsi;rdi
code-suffix: 64
flags: 64
gas: asz
@ -16079,7 +16079,7 @@ END
# Code: Xcryptofb_16
INSTRUCTION: a16 F3 0F A7 E8 | XCRYPTOFB | PADLOCK_ACE
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=ax;si;di
implied: crcw=[es:ax=Unknown] cr=[es:dx=Unknown];[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=si;di
code-suffix: 16
flags: 16 32
gas: asz
@ -16089,7 +16089,7 @@ END
# Code: Xcryptofb_32
INSTRUCTION: a32 F3 0F A7 E8 | XCRYPTOFB | PADLOCK_ACE
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=eax;esi;edi
implied: crcw=[es:eax=Unknown] cr=[es:edx=Unknown];[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=esi;edi
code-suffix: 32
gas: asz
intel: asz
@ -16098,7 +16098,7 @@ END
# Code: Xcryptofb_64
INSTRUCTION: a64 F3 0F A7 E8 | XCRYPTOFB | PADLOCK_ACE
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rax;rsi;rdi
implied: crcw=[es:rax=Unknown] cr=[es:rdx=Unknown];[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rsi;rdi
code-suffix: 64
flags: 64
gas: asz
@ -29833,3 +29833,77 @@ END
INSTRUCTION: VEX.256.66.0F38.W0 53 /r | VPDPWSSDS ymm1, ymm2, ymm3/m256 | AVX_VNNI
ops: rw=reg r=vvvv r=rm | Packed256_Int16
END
# Code: Ccs_hash_16
INSTRUCTION: a16 F3 0F A6 E8 | CCS_HASH | PADLOCK_GMI
# Some Zhaoxin CPUs support GMI, eg. ZX-C+, KX, KH
# GMI = GuoMi Instruction
# AFAIK, no public documentation, so I used https://github.com/openssl/openssl/pull/8706
# SM3 instruction
# PR comment: gm5 ccs_hash
#TODO: I assume reg/mem access is the same as xsha{1,256} instructions
#TODO: I assume rBX isn't written, only read
implied: cr=[es:si=Unknown] crcw=[es:di=Unknown] cw=si rcw=ax;cx cr=bx
code-suffix: 16
flags: 16 32
gas: asz
intel: asz
nasm: asz
END
# Code: Ccs_hash_32
INSTRUCTION: a32 F3 0F A6 E8 | CCS_HASH | PADLOCK_GMI
# See a16 version above for more info
implied: cr=[es:esi=Unknown] crcw=[es:edi=Unknown] cw=esi rcw=eax;ecx cr=ebx
code-suffix: 32
gas: asz
intel: asz
nasm: asz
END
# Code: Ccs_hash_64
INSTRUCTION: a64 F3 0F A6 E8 | CCS_HASH | PADLOCK_GMI
# See a16 version above for more info
implied: cr=[es:rsi=Unknown] crcw=[es:rdi=Unknown] cw=rsi rcw=rax;rcx cr=rbx
code-suffix: 64
flags: 64
gas: asz
intel: asz
nasm: asz
END
# Code: Ccs_encrypt_16
INSTRUCTION: a16 F3 0F A7 F0 | CCS_ENCRYPT | PADLOCK_GMI
# AFAIK, no public documentation, so I used https://github.com/openssl/openssl/pull/8706
# SM4 instruction
# PR comment: gx6 ccs_encrypt
#TODO: I assume rAX isn't written
implied: cr=[es:bx=Unknown];[es:si=Unknown] cw=[es:di=Unknown] rcw=cx cw=si;di cr=ax
code-suffix: 16
flags: 16 32
gas: asz
intel: asz
nasm: asz
END
# Code: Ccs_encrypt_32
INSTRUCTION: a32 F3 0F A7 F0 | CCS_ENCRYPT | PADLOCK_GMI
# See a16 version above for more info
implied: cr=[es:ebx=Unknown];[es:esi=Unknown] cw=[es:edi=Unknown] rcw=ecx cw=esi;edi cr=eax
code-suffix: 32
gas: asz
intel: asz
nasm: asz
END
# Code: Ccs_encrypt_64
INSTRUCTION: a64 F3 0F A7 F0 | CCS_ENCRYPT | PADLOCK_GMI
# See a16 version above for more info
implied: cr=[es:rbx=Unknown];[es:rsi=Unknown] cw=[es:rdi=Unknown] rcw=rcx cw=rsi;rdi cr=rax
code-suffix: 64
flags: 64
gas: asz
intel: asz
nasm: asz
END

14
src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests16.g.cs
View File

@ -1571,6 +1571,20 @@ namespace Iced.UnitTests.Intel.AssemblerTests {
TestAssembler(c => c.cbw(), Instruction.Create(Code.Cbw));
}
[Fact]
public void ccs_encrypt() {
{ // skip (Bitness == 64) not supported by this Assembler bitness
} /* else */ { // skip (Bitness >= 32) not supported by this Assembler bitness
} /* else */ TestAssembler(c => c.ccs_encrypt(), Instruction.Create(Code.Ccs_encrypt_16));
}
[Fact]
public void ccs_hash() {
{ // skip (Bitness == 64) not supported by this Assembler bitness
} /* else */ { // skip (Bitness >= 32) not supported by this Assembler bitness
} /* else */ TestAssembler(c => c.ccs_hash(), Instruction.Create(Code.Ccs_hash_16));
}
[Fact]
public void cdq() {
TestAssembler(c => c.cdq(), Instruction.Create(Code.Cdq));

16
src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests32.g.cs
View File

@ -1574,6 +1574,22 @@ namespace Iced.UnitTests.Intel.AssemblerTests {
TestAssembler(c => c.cbw(), Instruction.Create(Code.Cbw));
}
[Fact]
public void ccs_encrypt() {
{ // skip (Bitness == 64) not supported by this Assembler bitness
} /* else */ { /* if (Bitness >= 32) */
TestAssembler(c => c.ccs_encrypt(), Instruction.Create(Code.Ccs_encrypt_32));
} /* else skip (Bitness >= 32) not supported by this Assembler bitness */
}
[Fact]
public void ccs_hash() {
{ // skip (Bitness == 64) not supported by this Assembler bitness
} /* else */ { /* if (Bitness >= 32) */
TestAssembler(c => c.ccs_hash(), Instruction.Create(Code.Ccs_hash_32));
} /* else skip (Bitness >= 32) not supported by this Assembler bitness */
}
[Fact]
public void cdq() {
TestAssembler(c => c.cdq(), Instruction.Create(Code.Cdq));

14
src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTests64.g.cs
View File

@ -1874,6 +1874,20 @@ namespace Iced.UnitTests.Intel.AssemblerTests {
TestAssembler(c => c.cbw(), Instruction.Create(Code.Cbw));
}
[Fact]
public void ccs_encrypt() {
{ /* if (Bitness == 64) */
TestAssembler(c => c.ccs_encrypt(), Instruction.Create(Code.Ccs_encrypt_64));
} /* else skip (Bitness == 64) not supported by this Assembler bitness */
}
[Fact]
public void ccs_hash() {
{ /* if (Bitness == 64) */
TestAssembler(c => c.ccs_hash(), Instruction.Create(Code.Ccs_hash_64));
} /* else skip (Bitness == 64) not supported by this Assembler bitness */
}
[Fact]
public void cdq() {
TestAssembler(c => c.cdq(), Instruction.Create(Code.Cdq));

6
src/csharp/Intel/Iced.UnitTests/Intel/AssemblerTests/AssemblerTestsBase.cs
View File

@ -121,6 +121,12 @@ namespace Iced.UnitTests.Intel.AssemblerTests {
case Code.Xcryptofb_16:
case Code.Xcryptofb_32:
case Code.Xcryptofb_64:
case Code.Ccs_hash_16:
case Code.Ccs_hash_32:
case Code.Ccs_hash_64:
case Code.Ccs_encrypt_16:
case Code.Ccs_encrypt_32:
case Code.Ccs_encrypt_64:
// They're mandatory prefix instructions but the REP prefix isn't cleared since it's shown in disassembly
decodedInst.HasRepPrefix = false;
break;

8
src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Code.cs
View File

@ -35,7 +35,7 @@ namespace Iced.UnitTests.Intel {
static readonly Dictionary<string, Code> codeDict =
// GENERATOR-BEGIN: CodeHash
// ⚠️This was generated by GENERATOR!🦹‍♂️
new Dictionary<string, Code>(4312, StringComparer.Ordinal) {
new Dictionary<string, Code>(4318, StringComparer.Ordinal) {
{ "INVALID", Code.INVALID },
{ "DeclareByte", Code.DeclareByte },
{ "DeclareWord", Code.DeclareWord },
@ -4348,6 +4348,12 @@ namespace Iced.UnitTests.Intel {
{ "VEX_Vpdpwssd_ymm_ymm_ymmm256", Code.VEX_Vpdpwssd_ymm_ymm_ymmm256 },
{ "VEX_Vpdpwssds_xmm_xmm_xmmm128", Code.VEX_Vpdpwssds_xmm_xmm_xmmm128 },
{ "VEX_Vpdpwssds_ymm_ymm_ymmm256", Code.VEX_Vpdpwssds_ymm_ymm_ymmm256 },
{ "Ccs_hash_16", Code.Ccs_hash_16 },
{ "Ccs_hash_32", Code.Ccs_hash_32 },
{ "Ccs_hash_64", Code.Ccs_hash_64 },
{ "Ccs_encrypt_16", Code.Ccs_encrypt_16 },
{ "Ccs_encrypt_32", Code.Ccs_encrypt_32 },
{ "Ccs_encrypt_64", Code.Ccs_encrypt_64 },
};
// GENERATOR-END: CodeHash
}

3
src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.CpuidFeature.cs
View File

@ -34,7 +34,7 @@ namespace Iced.UnitTests.Intel {
static readonly Dictionary<string, CpuidFeature> cpuidFeatureDict =
// GENERATOR-BEGIN: CpuidFeatureHash
// ⚠️This was generated by GENERATOR!🦹‍♂️
new Dictionary<string, CpuidFeature>(155, StringComparer.Ordinal) {
new Dictionary<string, CpuidFeature>(156, StringComparer.Ordinal) {
{ "INTEL8086", CpuidFeature.INTEL8086 },
{ "INTEL8086_ONLY", CpuidFeature.INTEL8086_ONLY },
{ "INTEL186", CpuidFeature.INTEL186 },
@ -190,6 +190,7 @@ namespace Iced.UnitTests.Intel {
{ "UINTR", CpuidFeature.UINTR },
{ "HRESET", CpuidFeature.HRESET },
{ "AVX_VNNI", CpuidFeature.AVX_VNNI },
{ "PADLOCK_GMI", CpuidFeature.PADLOCK_GMI },
};
// GENERATOR-END: CpuidFeatureHash
}

4
src/csharp/Intel/Iced.UnitTests/Intel/ToEnumConverter.Mnemonic.cs
View File

@ -33,7 +33,7 @@ namespace Iced.UnitTests.Intel {
static readonly Dictionary<string, Mnemonic> mnemonicDict =
// GENERATOR-BEGIN: MnemonicHash
// ⚠️This was generated by GENERATOR!🦹‍♂️
new Dictionary<string, Mnemonic>(1627, StringComparer.Ordinal) {
new Dictionary<string, Mnemonic>(1629, StringComparer.Ordinal) {
{ "INVALID", Mnemonic.INVALID },
{ "Aaa", Mnemonic.Aaa },
{ "Aad", Mnemonic.Aad },
@ -1661,6 +1661,8 @@ namespace Iced.UnitTests.Intel {
{ "Stui", Mnemonic.Stui },
{ "Senduipi", Mnemonic.Senduipi },
{ "Hreset", Mnemonic.Hreset },
{ "Ccs_hash", Mnemonic.Ccs_hash },
{ "Ccs_encrypt", Mnemonic.Ccs_encrypt },
};
// GENERATOR-END: MnemonicHash
}

64
src/csharp/Intel/Iced/Intel/Assembler/Assembler.g.cs
View File

@ -5102,6 +5102,70 @@ namespace Iced.Intel {
op = Code.Cbw;
AddInstruction(Instruction.Create(op));
}
/// <summary>ccs_encrypt instruction.<br/>
/// <br/>
/// <c>CCS_ENCRYPT</c><br/>
/// <br/>
/// <c>a64 F3 0F A7 F0</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>64-bit</c><br/>
/// <br/>
/// <c>CCS_ENCRYPT</c><br/>
/// <br/>
/// <c>a32 F3 0F A7 F0</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32/64-bit</c><br/>
/// <br/>
/// <c>CCS_ENCRYPT</c><br/>
/// <br/>
/// <c>a16 F3 0F A7 F0</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32-bit</c></summary>
public void ccs_encrypt() {
Code op;
if (Bitness == 64) {
op = Code.Ccs_encrypt_64;
} else op = Bitness >= 32 ? Code.Ccs_encrypt_32 : Code.Ccs_encrypt_16;
AddInstruction(Instruction.Create(op));
}
/// <summary>ccs_hash instruction.<br/>
/// <br/>
/// <c>CCS_HASH</c><br/>
/// <br/>
/// <c>a64 F3 0F A6 E8</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>64-bit</c><br/>
/// <br/>
/// <c>CCS_HASH</c><br/>
/// <br/>
/// <c>a32 F3 0F A6 E8</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32/64-bit</c><br/>
/// <br/>
/// <c>CCS_HASH</c><br/>
/// <br/>
/// <c>a16 F3 0F A6 E8</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32-bit</c></summary>
public void ccs_hash() {
Code op;
if (Bitness == 64) {
op = Code.Ccs_hash_64;
} else op = Bitness >= 32 ? Code.Ccs_hash_32 : Code.Ccs_hash_16;
AddInstruction(Instruction.Create(op));
}
/// <summary>cdq instruction.<br/>
/// <br/>
/// <c>CDQ</c><br/>

48
src/csharp/Intel/Iced/Intel/Code.g.cs
View File

@ -34494,5 +34494,53 @@ namespace Iced.Intel {
/// <br/>
/// <c>16/32/64-bit</c></summary>
VEX_Vpdpwssds_ymm_ymm_ymmm256 = 4311,
/// <summary><c>CCS_HASH</c><br/>
/// <br/>
/// <c>a16 F3 0F A6 E8</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32-bit</c></summary>
Ccs_hash_16 = 4312,
/// <summary><c>CCS_HASH</c><br/>
/// <br/>
/// <c>a32 F3 0F A6 E8</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32/64-bit</c></summary>
Ccs_hash_32 = 4313,
/// <summary><c>CCS_HASH</c><br/>
/// <br/>
/// <c>a64 F3 0F A6 E8</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>64-bit</c></summary>
Ccs_hash_64 = 4314,
/// <summary><c>CCS_ENCRYPT</c><br/>
/// <br/>
/// <c>a16 F3 0F A7 F0</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32-bit</c></summary>
Ccs_encrypt_16 = 4315,
/// <summary><c>CCS_ENCRYPT</c><br/>
/// <br/>
/// <c>a32 F3 0F A7 F0</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>16/32/64-bit</c></summary>
Ccs_encrypt_32 = 4316,
/// <summary><c>CCS_ENCRYPT</c><br/>
/// <br/>
/// <c>a64 F3 0F A7 F0</c><br/>
/// <br/>
/// <c>PADLOCK_GMI</c><br/>
/// <br/>
/// <c>64-bit</c></summary>
Ccs_encrypt_64 = 4317,
}
}

2
src/csharp/Intel/Iced/Intel/CpuidFeature.g.cs
View File

@ -339,6 +339,8 @@ namespace Iced.Intel {
HRESET = 153,
/// <summary>CPUID.(EAX=07H, ECX=01H):EAX.AVX-VNNI[bit 4]</summary>
AVX_VNNI = 154,
/// <summary>CPUID.0C0000000H:EAX &gt;= 0C0000001H AND CPUID.0C0000001H:EDX.GMI[Bits 5:4] = 11B ([4] = exists, [5] = enabled)</summary>
PADLOCK_GMI = 155,
}
}
#endif

32
src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlersTables_Legacy.g.cs
View File

@ -2016,7 +2016,21 @@ namespace Iced.Intel.DecoderInternal {
// 17 = 0x11
0x05,// Dup
0x2F,// 47
0x17,// 23
0x06,// Null
// 40 = 0x28
0x12,// MandatoryPrefix4
0x03,// Invalid_NoModRM
0x03,// Invalid_NoModRM
0xAB,// Simple5
0xD8, 0x21,// Ccs_hash_16
0x03,// Invalid_NoModRM
0x00,// 0x0
// 41 = 0x29
0x05,// Dup
0x17,// 23
0x06,// Null
// handlers_Grp_0FA7_lo
@ -2106,7 +2120,21 @@ namespace Iced.Intel.DecoderInternal {
// 41 = 0x29
0x05,// Dup
0x17,// 23
0x07,// 7
0x06,// Null
// 48 = 0x30
0x12,// MandatoryPrefix4
0x03,// Invalid_NoModRM
0x03,// Invalid_NoModRM
0xAB,// Simple5
0xDB, 0x21,// Ccs_encrypt_16
0x03,// Invalid_NoModRM
0x00,// 0x0
// 49 = 0x31
0x05,// Dup
0x0F,// 15
0x06,// Null
// handlers_Grp_0FBA

24
src/csharp/Intel/Iced/Intel/EncoderInternal/EncoderData.g.cs
View File

@ -33,7 +33,7 @@ namespace Iced.Intel.EncoderInternal {
internal static readonly uint[] EncFlags3 = GetEncFlags3();
static uint[] GetEncFlags1() =>
new uint[4312] {
new uint[4318] {
0x00000000,// INVALID
0x00000000,// DeclareByte
0x00000000,// DeclareWord
@ -4346,10 +4346,16 @@ namespace Iced.Intel.EncoderInternal {
0x000096D9,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x00008594,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x000096D9,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x00000000,// Ccs_hash_16
0x00000000,// Ccs_hash_32
0x00000000,// Ccs_hash_64
0x00000000,// Ccs_encrypt_16
0x00000000,// Ccs_encrypt_32
0x00000000,// Ccs_encrypt_64
};
static uint[] GetEncFlags2() =>
new uint[4312] {
new uint[4318] {
0x00000000,// INVALID
0x00000000,// DeclareByte
0x00000000,// DeclareWord
@ -8662,10 +8668,16 @@ namespace Iced.Intel.EncoderInternal {
0x228C0052,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x220C0053,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x228C0053,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x2013A6E8,// Ccs_hash_16
0x2013A6E8,// Ccs_hash_32
0x2013A6E8,// Ccs_hash_64
0x2013A7F0,// Ccs_encrypt_16
0x2013A7F0,// Ccs_encrypt_32
0x2013A7F0,// Ccs_encrypt_64
};
static uint[] GetEncFlags3() =>
new uint[4312] {
new uint[4318] {
0x00030000,// INVALID
0x00030000,// DeclareByte
0x00030000,// DeclareWord
@ -12978,6 +12990,12 @@ namespace Iced.Intel.EncoderInternal {
0x00030001,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x00030001,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x00030001,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x00010020,// Ccs_hash_16
0x00030040,// Ccs_hash_32
0x00020060,// Ccs_hash_64
0x00010020,// Ccs_encrypt_16
0x00030040,// Ccs_encrypt_32
0x00020060,// Ccs_encrypt_64
};
}
}

16
src/csharp/Intel/Iced/Intel/EncoderInternal/OpCodeInfoData.g.cs
View File

@ -32,7 +32,7 @@ namespace Iced.Intel.EncoderInternal {
internal static readonly uint[] OpcFlags2 = GetOpcFlags2();
static uint[] GetOpcFlags1() =>
new uint[4312] {
new uint[4318] {
0x00000000,// INVALID
0x00000000,// DeclareByte
0x00000000,// DeclareWord
@ -4345,10 +4345,16 @@ namespace Iced.Intel.EncoderInternal {
0x00000000,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x00000000,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x00000000,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x00000000,// Ccs_hash_16
0x00000000,// Ccs_hash_32
0x00000000,// Ccs_hash_64
0x00000000,// Ccs_encrypt_16
0x00000000,// Ccs_encrypt_32
0x00000000,// Ccs_encrypt_64
};
static uint[] GetOpcFlags2() =>
new uint[4312] {
new uint[4318] {
0x1E003FFF,// INVALID
0x1E003FFF,// DeclareByte
0x1E003FFF,// DeclareWord
@ -8661,6 +8667,12 @@ namespace Iced.Intel.EncoderInternal {
0x1E003FFA,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x1E003FFA,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x1E003FFA,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0A003FFF,// Ccs_hash_16
0x1E003FFF,// Ccs_hash_32
0x14003FF0,// Ccs_hash_64
0x0A003FFF,// Ccs_encrypt_16
0x1E003FFF,// Ccs_encrypt_32
0x14003FF0,// Ccs_encrypt_64
};
}
}

20
src/csharp/Intel/Iced/Intel/FastFormatterInternal/FmtData.g.cs
View File

@ -14747,6 +14747,26 @@ namespace Iced.Intel.FastFormatterInternal {
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x03,// HasVPrefix, SameAsPrev
// Ccs_hash_16
0x00,// No flags set
0xCA, 0x0B,// 1482 = "ccs_hash"
// Ccs_hash_32
0x02,// SameAsPrev
// Ccs_hash_64
0x02,// SameAsPrev
// Ccs_encrypt_16
0x00,// No flags set
0xCB, 0x0B,// 1483 = "ccs_encrypt"
// Ccs_encrypt_32
0x02,// SameAsPrev
// Ccs_encrypt_64
0x02,// SameAsPrev
};
}
}

4
src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterStringsTable.g.cs
View File

@ -29,7 +29,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
namespace Iced.Intel.FormatterInternal {
static partial class FormatterStringsTable {
const int MaxStringLength = 18;
const int StringsCount = 1482;
const int StringsCount = 1484;
#if HAS_SPAN
static System.ReadOnlySpan<byte> GetSerializedStrings() =>
#else
@ -1518,6 +1518,8 @@ namespace Iced.Intel.FormatterInternal {
0x04, 0x73, 0x74, 0x75, 0x69,// stui
0x08, 0x73, 0x65, 0x6E, 0x64, 0x75, 0x69, 0x70, 0x69,// senduipi
0x06, 0x68, 0x72, 0x65, 0x73, 0x65, 0x74,// hreset
0x08, 0x63, 0x63, 0x73, 0x5F, 0x68, 0x61, 0x73, 0x68,// ccs_hash
0x0B, 0x63, 0x63, 0x73, 0x5F, 0x65, 0x6E, 0x63, 0x72, 0x79, 0x70, 0x74,// ccs_encrypt
};
}
}

6
src/csharp/Intel/Iced/Intel/FormatterInternal/FormatterUtils.cs
View File

@ -332,6 +332,12 @@ namespace Iced.Intel.FormatterInternal {
case Code.Xcryptofb_16:
case Code.Xcryptofb_32:
case Code.Xcryptofb_64:
case Code.Ccs_hash_16:
case Code.Ccs_hash_32:
case Code.Ccs_hash_64:
case Code.Ccs_encrypt_16:
case Code.Ccs_encrypt_32:
case Code.Ccs_encrypt_64:
return true;
default:

30
src/csharp/Intel/Iced/Intel/GasFormatterInternal/InstrInfos.g.cs
View File

@ -17966,6 +17966,36 @@ namespace Iced.Intel.GasFormatterInternal {
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x07,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x10,// 0x10
// Ccs_hash_32
0x07,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x20,// 0x20
// Ccs_hash_64
0x07,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x40,// 0x40
// Ccs_encrypt_16
0x07,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x10,// 0x10
// Ccs_encrypt_32
0x07,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x20,// 0x20
// Ccs_encrypt_64
0x07,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x40,// 0x40
};
}
}

4
src/csharp/Intel/Iced/Intel/IcedConstants.g.cs
View File

@ -30,7 +30,7 @@ namespace Iced.Intel {
internal const int MaxOpCount = 5;
internal const int MaxInstructionLength = 15;
internal const int RegisterBits = 8;
internal const int NumberOfCodeValues = 4312;
internal const int NumberOfCodeValues = 4318;
internal const int NumberOfRegisters = 249;
internal const int NumberOfMemorySizes = 141;
internal const int NumberOfEncodingKinds = 5;
@ -44,7 +44,7 @@ namespace Iced.Intel {
internal const Register YMM_last = Register.YMM31;
internal const Register ZMM_last = Register.ZMM31;
internal const Register TMM_last = Register.TMM7;
internal const int MaxCpuidFeatureInternalValues = 175;
internal const int MaxCpuidFeatureInternalValues = 176;
internal const MemorySize FirstBroadcastMemorySize = MemorySize.Broadcast64_UInt32;
}
}

132
src/csharp/Intel/Iced/Intel/InstructionInfoFactory.cs
View File

@ -1102,57 +1102,51 @@ namespace Iced.Intel {
AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRax_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx:
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.SI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code16, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.AX, OpAccess.CondRead);
AddRegister(flags, Register.SI, OpAccess.CondRead);
AddRegister(flags, Register.DI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.AX, OpAccess.CondWrite);
AddRegister(flags, Register.SI, OpAccess.CondWrite);
AddRegister(flags, Register.DI, OpAccess.CondWrite);
AddRegister(flags, Register.AX, OpAccess.ReadCondWrite);
AddRegister(flags, Register.CX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CReax_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx:
case ImpliedAccess.t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.ESI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code32, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.EAX, OpAccess.CondRead);
AddRegister(flags, Register.ESI, OpAccess.CondRead);
AddRegister(flags, Register.EDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.EAX, OpAccess.CondWrite);
AddRegister(flags, Register.ESI, OpAccess.CondWrite);
AddRegister(flags, Register.EDI, OpAccess.CondWrite);
AddRegister(flags, Register.EAX, OpAccess.ReadCondWrite);
AddRegister(flags, Register.ECX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRrax_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx:
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.RSI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code64, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.RAX, OpAccess.CondRead);
AddRegister(flags, Register.RSI, OpAccess.CondRead);
AddRegister(flags, Register.RDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.RAX, OpAccess.CondWrite);
AddRegister(flags, Register.RSI, OpAccess.CondWrite);
AddRegister(flags, Register.RDI, OpAccess.CondWrite);
AddRegister(flags, Register.RAX, OpAccess.ReadCondWrite);
AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite);
}
break;
@ -1234,7 +1228,7 @@ namespace Iced.Intel {
AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx:
case ImpliedAccess.t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.AX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.DX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
@ -1251,13 +1245,12 @@ namespace Iced.Intel {
AddRegister(flags, Register.DI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.AX, OpAccess.CondWrite);
AddRegister(flags, Register.SI, OpAccess.CondWrite);
AddRegister(flags, Register.DI, OpAccess.CondWrite);
AddRegister(flags, Register.CX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx:
case ImpliedAccess.t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.EAX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.EDX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
@ -1274,13 +1267,12 @@ namespace Iced.Intel {
AddRegister(flags, Register.EDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.EAX, OpAccess.CondWrite);
AddRegister(flags, Register.ESI, OpAccess.CondWrite);
AddRegister(flags, Register.EDI, OpAccess.CondWrite);
AddRegister(flags, Register.ECX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx:
case ImpliedAccess.t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.RAX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RDX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
@ -1297,7 +1289,6 @@ namespace Iced.Intel {
AddRegister(flags, Register.RDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.RAX, OpAccess.CondWrite);
AddRegister(flags, Register.RSI, OpAccess.CondWrite);
AddRegister(flags, Register.RDI, OpAccess.CondWrite);
AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite);
@ -1584,6 +1575,111 @@ namespace Iced.Intel {
case ImpliedAccess.t_pop3x8:
CommandPop(instruction, flags, 3, 8);
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRbx_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.SI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code16, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.BX, OpAccess.CondRead);
AddRegister(flags, Register.SI, OpAccess.CondRead);
AddRegister(flags, Register.DI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.SI, OpAccess.CondWrite);
AddRegister(flags, Register.AX, OpAccess.ReadCondWrite);
AddRegister(flags, Register.CX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRebx_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.ESI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code32, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.EBX, OpAccess.CondRead);
AddRegister(flags, Register.ESI, OpAccess.CondRead);
AddRegister(flags, Register.EDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.ESI, OpAccess.CondWrite);
AddRegister(flags, Register.EAX, OpAccess.ReadCondWrite);
AddRegister(flags, Register.ECX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRrbx_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.RSI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code64, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.RBX, OpAccess.CondRead);
AddRegister(flags, Register.RSI, OpAccess.CondRead);
AddRegister(flags, Register.RDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.RSI, OpAccess.CondWrite);
AddRegister(flags, Register.RAX, OpAccess.ReadCondWrite);
AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRax_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.BX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.SI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code16, 0);
AddMemory(Register.ES, Register.DI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code16, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.AX, OpAccess.CondRead);
AddRegister(flags, Register.BX, OpAccess.CondRead);
AddRegister(flags, Register.SI, OpAccess.CondRead);
AddRegister(flags, Register.DI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.SI, OpAccess.CondWrite);
AddRegister(flags, Register.DI, OpAccess.CondWrite);
AddRegister(flags, Register.CX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CReax_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.EBX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.ESI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code32, 0);
AddMemory(Register.ES, Register.EDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code32, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.EAX, OpAccess.CondRead);
AddRegister(flags, Register.EBX, OpAccess.CondRead);
AddRegister(flags, Register.ESI, OpAccess.CondRead);
AddRegister(flags, Register.EDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.ESI, OpAccess.CondWrite);
AddRegister(flags, Register.EDI, OpAccess.CondWrite);
AddRegister(flags, Register.ECX, OpAccess.ReadCondWrite);
}
break;
case ImpliedAccess.t_CRmem_CRmem_CWmem_CRrax_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx:
if ((flags & Flags.NoMemoryUsage) == 0) {
AddMemory(Register.ES, Register.RBX, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RSI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondRead, CodeSize.Code64, 0);
AddMemory(Register.ES, Register.RDI, Register.None, 1, 0x0, MemorySize.Unknown, OpAccess.CondWrite, CodeSize.Code64, 0);
}
if ((flags & Flags.NoRegisterUsage) == 0) {
AddRegister(flags, Register.RAX, OpAccess.CondRead);
AddRegister(flags, Register.RBX, OpAccess.CondRead);
AddRegister(flags, Register.RSI, OpAccess.CondRead);
AddRegister(flags, Register.RDI, OpAccess.CondRead);
if ((flags & Flags.Is64Bit) == 0)
AddRegister(flags, Register.ES, OpAccess.CondRead);
AddRegister(flags, Register.RSI, OpAccess.CondWrite);
AddRegister(flags, Register.RDI, OpAccess.CondWrite);
AddRegister(flags, Register.RCX, OpAccess.ReadCondWrite);
}
break;
// GENERATOR-END: ImpliedAccessHandler
default:

1
src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternal.g.cs
View File

@ -203,6 +203,7 @@ namespace Iced.Intel.InstructionInfoInternal {
UINTR,
HRESET,
AVX_VNNI,
PADLOCK_GMI,
}
}
#endif

1
src/csharp/Intel/Iced/Intel/InstructionInfoInternal/CpuidFeatureInternalData.g.cs
View File

@ -233,6 +233,7 @@ namespace Iced.Intel.InstructionInfoInternal {
0x98,// UINTR
0x99,// HRESET
0x9A,// AVX_VNNI
0x9B,// PADLOCK_GMI
};
}
}

18
src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InfoHandlerFlags.cs
View File

@ -282,9 +282,9 @@ namespace Iced.Intel.InstructionInfoInternal {
t_CRmem_CRsi_CReax_CRes_CWeax_CWedx_RCWecx,
t_CRmem_CReax_CResi_CRes_CWeax_CWedx_RCWecx,
t_CRmem_CReax_CRrsi_CRes_CWeax_CWedx_RCWrcx,
t_CRmem_CRmem_CWmem_CRax_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CWmem_CReax_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CWmem_CRrax_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx,
t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx,
t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx,
t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx,
t_Rcl_Rax,
t_Rcl_Reax,
t_xstore2,
@ -293,9 +293,9 @@ namespace Iced.Intel.InstructionInfoInternal {
t_CRmem_CRmem_CRmem_CWmem_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CRmem_CWmem_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CRmem_CWmem_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
t_RCWal,
t_RCWax,
t_RCWeax,
@ -341,6 +341,12 @@ namespace Iced.Intel.InstructionInfoInternal {
t_Wxmm1_Wxmm2_RWxmm0_Wxmm4TOxmm6,
t_RWxmm0_RWxmm1_Wxmm2TOxmm6,
t_pop3x8,
t_CRmem_CRmem_CWmem_CRbx_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx,
t_CRmem_CRmem_CWmem_CRebx_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx,
t_CRmem_CRmem_CWmem_CRrbx_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx,
t_CRmem_CRmem_CWmem_CRax_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CWmem_CReax_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CWmem_CRrax_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
}
// GENERATOR-END: ImpliedAccess

8
src/csharp/Intel/Iced/Intel/InstructionInfoInternal/InstrInfoTable.g.cs
View File

@ -28,7 +28,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#if INSTR_INFO
namespace Iced.Intel.InstructionInfoInternal {
static class InstrInfoTable {
internal static readonly uint[] Data = new uint[8624] {
internal static readonly uint[] Data = new uint[8636] {
0x00000000, 0x00900000,// INVALID
0x00000000, 0x00900000,// DeclareByte
0x00000000, 0x00900000,// DeclareWord
@ -4341,6 +4341,12 @@ namespace Iced.Intel.InstructionInfoInternal {
0x000000B6, 0xAE000001,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x000000B6, 0xAE000001,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x000000B6, 0xAE000001,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0B600000, 0xAF000000,// Ccs_hash_16
0x0B700000, 0xAF000000,// Ccs_hash_32
0x0B800000, 0xAF000000,// Ccs_hash_64
0x0B900000, 0xAF000000,// Ccs_encrypt_16
0x0BA00000, 0xAF000000,// Ccs_encrypt_32
0x0BB00000, 0xAF000000,// Ccs_encrypt_64
};
}
}

12
src/csharp/Intel/Iced/Intel/InstructionMemorySizes.g.cs
View File

@ -4346,6 +4346,12 @@ namespace Iced.Intel {
(byte)MemorySize.Packed256_Int16,// VEX_Vpdpwssd_ymm_ymm_ymmm256
(byte)MemorySize.Packed128_Int16,// VEX_Vpdpwssds_xmm_xmm_xmmm128
(byte)MemorySize.Packed256_Int16,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0,// Ccs_hash_16
0,// Ccs_hash_32
0,// Ccs_hash_64
0,// Ccs_encrypt_16
0,// Ccs_encrypt_32
0,// Ccs_encrypt_64
0,// INVALID
0,// DeclareByte
0,// DeclareWord
@ -8658,6 +8664,12 @@ namespace Iced.Intel {
0,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0,// Ccs_hash_16
0,// Ccs_hash_32
0,// Ccs_hash_64
0,// Ccs_encrypt_16
0,// Ccs_encrypt_32
0,// Ccs_encrypt_64
};
}
}

6
src/csharp/Intel/Iced/Intel/InstructionOpCounts.g.cs
View File

@ -4344,6 +4344,12 @@ namespace Iced.Intel {
3,// VEX_Vpdpwssd_ymm_ymm_ymmm256
3,// VEX_Vpdpwssds_xmm_xmm_xmmm128
3,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0,// Ccs_hash_16
0,// Ccs_hash_32
0,// Ccs_hash_64
0,// Ccs_encrypt_16
0,// Ccs_encrypt_32
0,// Ccs_encrypt_64
};
}
}

30
src/csharp/Intel/Iced/Intel/IntelFormatterInternal/InstrInfos.g.cs
View File

@ -16109,6 +16109,36 @@ namespace Iced.Intel.IntelFormatterInternal {
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x03,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x10,// 0x10
// Ccs_hash_32
0x03,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x20,// 0x20
// Ccs_hash_64
0x03,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x40,// 0x40
// Ccs_encrypt_16
0x03,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x10,// 0x10
// Ccs_encrypt_32
0x03,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x20,// 0x20
// Ccs_encrypt_64
0x03,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x40,// 0x40
};
}
}

20
src/csharp/Intel/Iced/Intel/MasmFormatterInternal/InstrInfos.g.cs
View File

@ -16180,6 +16180,26 @@ namespace Iced.Intel.MasmFormatterInternal {
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x01,// Normal_1
0xCA, 0x0B,// 1482 = "ccs_hash"
// Ccs_hash_32
0x00,// Previous
// Ccs_hash_64
0x00,// Previous
// Ccs_encrypt_16
0x01,// Normal_1
0xCB, 0x0B,// 1483 = "ccs_encrypt"
// Ccs_encrypt_32
0x00,// Previous
// Ccs_encrypt_64
0x00,// Previous
};
}
}

2
src/csharp/Intel/Iced/Intel/Mnemonic.g.cs
View File

@ -1656,6 +1656,8 @@ namespace Iced.Intel {
Stui = 1624,
Senduipi = 1625,
Hreset = 1626,
Ccs_hash = 1627,
Ccs_encrypt = 1628,
}
#pragma warning restore CS1591 // Missing XML comment for publicly visible type or member
}

6
src/csharp/Intel/Iced/Intel/MnemonicUtilsData.g.cs
View File

@ -4340,6 +4340,12 @@ namespace Iced.Intel {
(ushort)Mnemonic.Vpdpwssd,// VEX_Vpdpwssd_ymm_ymm_ymmm256
(ushort)Mnemonic.Vpdpwssds,// VEX_Vpdpwssds_xmm_xmm_xmmm128
(ushort)Mnemonic.Vpdpwssds,// VEX_Vpdpwssds_ymm_ymm_ymmm256
(ushort)Mnemonic.Ccs_hash,// Ccs_hash_16
(ushort)Mnemonic.Ccs_hash,// Ccs_hash_32
(ushort)Mnemonic.Ccs_hash,// Ccs_hash_64
(ushort)Mnemonic.Ccs_encrypt,// Ccs_encrypt_16
(ushort)Mnemonic.Ccs_encrypt,// Ccs_encrypt_32
(ushort)Mnemonic.Ccs_encrypt,// Ccs_encrypt_64
};
}
}

30
src/csharp/Intel/Iced/Intel/NasmFormatterInternal/InstrInfos.g.cs
View File

@ -16622,6 +16622,36 @@ namespace Iced.Intel.NasmFormatterInternal {
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x04,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x10,// 0x10
// Ccs_hash_32
0x04,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x20,// 0x20
// Ccs_hash_64
0x04,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x40,// 0x40
// Ccs_encrypt_16
0x04,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x10,// 0x10
// Ccs_encrypt_32
0x04,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x20,// 0x20
// Ccs_encrypt_64
0x04,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x40,// 0x40
};
}
}

1
src/csharp/Intel/IcedFuzzer/IcedFuzzer/Program.cs
View File

@ -365,6 +365,7 @@ namespace IcedFuzzer {
options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_PHE);
options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_PMM);
options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_RNG);
options.OpCodeInfoOptions.Filter.ExcludeCpuid.Add(CpuidFeature.PADLOCK_GMI);
break;
case "--no-unused-tables":

6
src/rust/iced-x86-js/src/code.rs
View File

@ -4343,6 +4343,12 @@ pub enum Code {
VEX_Vpdpwssd_ymm_ymm_ymmm256 = 4309,
VEX_Vpdpwssds_xmm_xmm_xmmm128 = 4310,
VEX_Vpdpwssds_ymm_ymm_ymmm256 = 4311,
Ccs_hash_16 = 4312,
Ccs_hash_32 = 4313,
Ccs_hash_64 = 4314,
Ccs_encrypt_16 = 4315,
Ccs_encrypt_32 = 4316,
Ccs_encrypt_64 = 4317,
}
// GENERATOR-END: Enum

2
src/rust/iced-x86-js/src/cpuid_feature.rs
View File

@ -346,5 +346,7 @@ pub enum CpuidFeature {
HRESET = 153,
/// CPUID.(EAX=07H, ECX=01H):EAX.AVX-VNNI\[bit 4\]
AVX_VNNI = 154,
/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.GMI\[Bits 5:4\] = 11B (\[4\] = exists, \[5\] = enabled)
PADLOCK_GMI = 155,
}
// GENERATOR-END: Enum

2
src/rust/iced-x86-js/src/mnemonic.rs
View File

@ -1658,6 +1658,8 @@ pub enum Mnemonic {
Stui = 1624,
Senduipi = 1625,
Hreset = 1626,
Ccs_hash = 1627,
Ccs_encrypt = 1628,
}
// GENERATOR-END: Enum

56
src/rust/iced-x86/src/code.rs
View File

@ -34502,9 +34502,57 @@ pub enum Code {
///
/// `16/32/64-bit`
VEX_Vpdpwssds_ymm_ymm_ymmm256 = 4311,
/// `CCS_HASH`
///
/// `a16 F3 0F A6 E8`
///
/// `PADLOCK_GMI`
///
/// `16/32-bit`
Ccs_hash_16 = 4312,
/// `CCS_HASH`
///
/// `a32 F3 0F A6 E8`
///
/// `PADLOCK_GMI`
///
/// `16/32/64-bit`
Ccs_hash_32 = 4313,
/// `CCS_HASH`
///
/// `a64 F3 0F A6 E8`
///
/// `PADLOCK_GMI`
///
/// `64-bit`
Ccs_hash_64 = 4314,
/// `CCS_ENCRYPT`
///
/// `a16 F3 0F A7 F0`
///
/// `PADLOCK_GMI`
///
/// `16/32-bit`
Ccs_encrypt_16 = 4315,
/// `CCS_ENCRYPT`
///
/// `a32 F3 0F A7 F0`
///
/// `PADLOCK_GMI`
///
/// `16/32/64-bit`
Ccs_encrypt_32 = 4316,
/// `CCS_ENCRYPT`
///
/// `a64 F3 0F A7 F0`
///
/// `PADLOCK_GMI`
///
/// `64-bit`
Ccs_encrypt_64 = 4317,
}
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_CODE: [&str; 4312] = [
static GEN_DEBUG_CODE: [&str; 4318] = [
"INVALID",
"DeclareByte",
"DeclareWord",
@ -38817,6 +38865,12 @@ static GEN_DEBUG_CODE: [&str; 4312] = [
"VEX_Vpdpwssd_ymm_ymm_ymmm256",
"VEX_Vpdpwssds_xmm_xmm_xmmm128",
"VEX_Vpdpwssds_ymm_ymm_ymmm256",
"Ccs_hash_16",
"Ccs_hash_32",
"Ccs_hash_64",
"Ccs_encrypt_16",
"Ccs_encrypt_32",
"Ccs_encrypt_64",
];
impl fmt::Debug for Code {
#[inline]

32
src/rust/iced-x86/src/decoder/table_de/data_legacy.rs
View File

@ -2007,7 +2007,21 @@ pub(super) static TBL_DATA: &[u8] = &[
// 17 = 0x11
0x05,// Dup
0x2F,// 47
0x17,// 23
0x06,// Null
// 40 = 0x28
0x12,// MandatoryPrefix4
0x03,// Invalid_NoModRM
0x03,// Invalid_NoModRM
0xAB,// Simple5
0xD8, 0x21,// Ccs_hash_16
0x03,// Invalid_NoModRM
0x00,// 0x0
// 41 = 0x29
0x05,// Dup
0x17,// 23
0x06,// Null
// handlers_Grp_0FA7_lo
@ -2097,7 +2111,21 @@ pub(super) static TBL_DATA: &[u8] = &[
// 41 = 0x29
0x05,// Dup
0x17,// 23
0x07,// 7
0x06,// Null
// 48 = 0x30
0x12,// MandatoryPrefix4
0x03,// Invalid_NoModRM
0x03,// Invalid_NoModRM
0xAB,// Simple5
0xDB, 0x21,// Ccs_encrypt_16
0x03,// Invalid_NoModRM
0x00,// 0x0
// 49 = 0x31
0x05,// Dup
0x0F,// 15
0x06,// Null
// handlers_Grp_0FBA

24
src/rust/iced-x86/src/encoder/encoder_data.rs
View File

@ -24,7 +24,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ⚠️This file was generated by GENERATOR!🦹‍♂️
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static ENC_FLAGS1: [u32; 4312] = [
pub(super) static ENC_FLAGS1: [u32; 4318] = [
0x0000_0000,// INVALID
0x0000_0000,// DeclareByte
0x0000_0000,// DeclareWord
@ -4337,9 +4337,15 @@ pub(super) static ENC_FLAGS1: [u32; 4312] = [
0x0000_96D9,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x0000_8594,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x0000_96D9,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0000_0000,// Ccs_hash_16
0x0000_0000,// Ccs_hash_32
0x0000_0000,// Ccs_hash_64
0x0000_0000,// Ccs_encrypt_16
0x0000_0000,// Ccs_encrypt_32
0x0000_0000,// Ccs_encrypt_64
];
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static ENC_FLAGS2: [u32; 4312] = [
pub(super) static ENC_FLAGS2: [u32; 4318] = [
0x0000_0000,// INVALID
0x0000_0000,// DeclareByte
0x0000_0000,// DeclareWord
@ -8652,9 +8658,15 @@ pub(super) static ENC_FLAGS2: [u32; 4312] = [
0x228C_0052,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x220C_0053,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x228C_0053,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x2013_A6E8,// Ccs_hash_16
0x2013_A6E8,// Ccs_hash_32
0x2013_A6E8,// Ccs_hash_64
0x2013_A7F0,// Ccs_encrypt_16
0x2013_A7F0,// Ccs_encrypt_32
0x2013_A7F0,// Ccs_encrypt_64
];
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static ENC_FLAGS3: [u32; 4312] = [
pub(super) static ENC_FLAGS3: [u32; 4318] = [
0x0003_0000,// INVALID
0x0003_0000,// DeclareByte
0x0003_0000,// DeclareWord
@ -12967,4 +12979,10 @@ pub(super) static ENC_FLAGS3: [u32; 4312] = [
0x0003_0001,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x0003_0001,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x0003_0001,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0001_0020,// Ccs_hash_16
0x0003_0040,// Ccs_hash_32
0x0002_0060,// Ccs_hash_64
0x0001_0020,// Ccs_encrypt_16
0x0003_0040,// Ccs_encrypt_32
0x0002_0060,// Ccs_encrypt_64
];

4
src/rust/iced-x86/src/encoder/mnemonic_str_tbl.rs
View File

@ -24,7 +24,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ⚠️This file was generated by GENERATOR!🦹‍♂️
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static TO_MNEMONIC_STR: [&str; 1627] = [
pub(super) static TO_MNEMONIC_STR: [&str; 1629] = [
"invalid",
"aaa",
"aad",
@ -1652,4 +1652,6 @@ pub(super) static TO_MNEMONIC_STR: [&str; 1627] = [
"stui",
"senduipi",
"hreset",
"ccs_hash",
"ccs_encrypt",
];

16
src/rust/iced-x86/src/encoder/op_code_data.rs
View File

@ -24,7 +24,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ⚠️This file was generated by GENERATOR!🦹‍♂️
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static OPC_FLAGS1: [u32; 4312] = [
pub(super) static OPC_FLAGS1: [u32; 4318] = [
0x0000_0000,// INVALID
0x0000_0000,// DeclareByte
0x0000_0000,// DeclareWord
@ -4337,9 +4337,15 @@ pub(super) static OPC_FLAGS1: [u32; 4312] = [
0x0000_0000,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x0000_0000,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x0000_0000,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0000_0000,// Ccs_hash_16
0x0000_0000,// Ccs_hash_32
0x0000_0000,// Ccs_hash_64
0x0000_0000,// Ccs_encrypt_16
0x0000_0000,// Ccs_encrypt_32
0x0000_0000,// Ccs_encrypt_64
];
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static OPC_FLAGS2: [u32; 4312] = [
pub(super) static OPC_FLAGS2: [u32; 4318] = [
0x1E00_3FFF,// INVALID
0x1E00_3FFF,// DeclareByte
0x1E00_3FFF,// DeclareWord
@ -8652,4 +8658,10 @@ pub(super) static OPC_FLAGS2: [u32; 4312] = [
0x1E00_3FFA,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x1E00_3FFA,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x1E00_3FFA,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0A00_3FFF,// Ccs_hash_16
0x1E00_3FFF,// Ccs_hash_32
0x1400_3FF0,// Ccs_hash_64
0x0A00_3FFF,// Ccs_encrypt_16
0x1E00_3FFF,// Ccs_encrypt_32
0x1400_3FF0,// Ccs_encrypt_64
];

5
src/rust/iced-x86/src/enums.rs
View File

@ -1233,10 +1233,12 @@ pub enum CpuidFeature {
HRESET = 153,
/// CPUID.(EAX=07H, ECX=01H):EAX.AVX-VNNI\[bit 4\]
AVX_VNNI = 154,
/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.GMI\[Bits 5:4\] = 11B (\[4\] = exists, \[5\] = enabled)
PADLOCK_GMI = 155,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_CPUID_FEATURE: [&str; 155] = [
static GEN_DEBUG_CPUID_FEATURE: [&str; 156] = [
"INTEL8086",
"INTEL8086_ONLY",
"INTEL186",
@ -1392,6 +1394,7 @@ static GEN_DEBUG_CPUID_FEATURE: [&str; 155] = [
"UINTR",
"HRESET",
"AVX_VNNI",
"PADLOCK_GMI",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for CpuidFeature {

20
src/rust/iced-x86/src/formatter/fast/fmt_data.rs
View File

@ -14738,4 +14738,24 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x03,// HasVPrefix, SameAsPrev
// Ccs_hash_16
0x00,// No flags set
0xCA, 0x0B,// 1482 = "ccs_hash"
// Ccs_hash_32
0x02,// SameAsPrev
// Ccs_hash_64
0x02,// SameAsPrev
// Ccs_encrypt_16
0x00,// No flags set
0xCB, 0x0B,// 1483 = "ccs_encrypt"
// Ccs_encrypt_32
0x02,// SameAsPrev
// Ccs_encrypt_64
0x02,// SameAsPrev
];

8
src/rust/iced-x86/src/formatter/fmt_utils_all.rs
View File

@ -78,7 +78,13 @@ pub(super) fn is_rep_repe_repne_instruction(code: Code) -> bool {
| Code::Xcryptcfb_64
| Code::Xcryptofb_16
| Code::Xcryptofb_32
| Code::Xcryptofb_64 => true,
| Code::Xcryptofb_64
| Code::Ccs_hash_16
| Code::Ccs_hash_32
| Code::Ccs_hash_64
| Code::Ccs_encrypt_16
| Code::Ccs_encrypt_32
| Code::Ccs_encrypt_64 => true,
_ => false,
}

30
src/rust/iced-x86/src/formatter/gas/fmt_data.rs
View File

@ -17957,4 +17957,34 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x07,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x10,// 0x10
// Ccs_hash_32
0x07,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x20,// 0x20
// Ccs_hash_64
0x07,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x40,// 0x40
// Ccs_encrypt_16
0x07,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x10,// 0x10
// Ccs_encrypt_32
0x07,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x20,// 0x20
// Ccs_encrypt_64
0x07,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x40,// 0x40
];

30
src/rust/iced-x86/src/formatter/intel/fmt_data.rs
View File

@ -16100,4 +16100,34 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x03,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x10,// 0x10
// Ccs_hash_32
0x03,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x20,// 0x20
// Ccs_hash_64
0x03,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x40,// 0x40
// Ccs_encrypt_16
0x03,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x10,// 0x10
// Ccs_encrypt_32
0x03,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x20,// 0x20
// Ccs_encrypt_64
0x03,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x40,// 0x40
];

20
src/rust/iced-x86/src/formatter/masm/fmt_data.rs
View File

@ -16171,4 +16171,24 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x01,// Normal_1
0xCA, 0x0B,// 1482 = "ccs_hash"
// Ccs_hash_32
0x00,// Previous
// Ccs_hash_64
0x00,// Previous
// Ccs_encrypt_16
0x01,// Normal_1
0xCB, 0x0B,// 1483 = "ccs_encrypt"
// Ccs_encrypt_32
0x00,// Previous
// Ccs_encrypt_64
0x00,// Previous
];

30
src/rust/iced-x86/src/formatter/nasm/fmt_data.rs
View File

@ -16613,4 +16613,34 @@ pub(super) static FORMATTER_TBL_DATA: &[u8] = &[
// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x80,// 'v', Previous
// Ccs_hash_16
0x04,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x10,// 0x10
// Ccs_hash_32
0x04,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x20,// 0x20
// Ccs_hash_64
0x04,// asz
0xCA, 0x0B,// 1482 = "ccs_hash"
0x40,// 0x40
// Ccs_encrypt_16
0x04,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x10,// 0x10
// Ccs_encrypt_32
0x04,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x20,// 0x20
// Ccs_encrypt_64
0x04,// asz
0xCB, 0x0B,// 1483 = "ccs_encrypt"
0x40,// 0x40
];

6
src/rust/iced-x86/src/formatter/strings_data.rs
View File

@ -23,10 +23,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ⚠️This file was generated by GENERATOR!🦹‍♂️
pub(super) const STRINGS_COUNT: usize = 1482;
pub(super) const STRINGS_COUNT: usize = 1484;
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(super) static STRINGS_TBL_DATA: [u8; 11414] = [
pub(super) static STRINGS_TBL_DATA: [u8; 11435] = [
0x03, 0x6D, 0x6F, 0x76,// mov
0x03, 0x6E, 0x6F, 0x70,// nop
0x04, 0x70, 0x75, 0x73, 0x68,// push
@ -1509,4 +1509,6 @@ pub(super) static STRINGS_TBL_DATA: [u8; 11414] = [
0x04, 0x73, 0x74, 0x75, 0x69,// stui
0x08, 0x73, 0x65, 0x6E, 0x64, 0x75, 0x69, 0x70, 0x69,// senduipi
0x06, 0x68, 0x72, 0x65, 0x73, 0x65, 0x74,// hreset
0x08, 0x63, 0x63, 0x73, 0x5F, 0x68, 0x61, 0x73, 0x68,// ccs_hash
0x0B, 0x63, 0x63, 0x73, 0x5F, 0x65, 0x6E, 0x63, 0x72, 0x79, 0x70, 0x74,// ccs_encrypt
];

4
src/rust/iced-x86/src/iced_constants.rs
View File

@ -31,7 +31,7 @@ impl IcedConstants {
pub(crate) const MAX_OP_COUNT: usize = 5;
pub(crate) const MAX_INSTRUCTION_LENGTH: usize = 15;
pub(crate) const REGISTER_BITS: u32 = 8;
pub(crate) const NUMBER_OF_CODE_VALUES: usize = 4312;
pub(crate) const NUMBER_OF_CODE_VALUES: usize = 4318;
pub(crate) const NUMBER_OF_REGISTERS: usize = 249;
pub(crate) const NUMBER_OF_MEMORY_SIZES: usize = 141;
pub(crate) const NUMBER_OF_ENCODING_KINDS: usize = 5;
@ -45,7 +45,7 @@ impl IcedConstants {
pub(crate) const YMM_LAST: Register = Register::YMM31;
pub(crate) const ZMM_LAST: Register = Register::ZMM31;
pub(crate) const TMM_LAST: Register = Register::TMM7;
pub(crate) const MAX_CPUID_FEATURE_INTERNAL_VALUES: usize = 175;
pub(crate) const MAX_CPUID_FEATURE_INTERNAL_VALUES: usize = 176;
pub(crate) const FIRST_BROADCAST_MEMORY_SIZE: MemorySize = MemorySize::Broadcast64_UInt32;
}
// GENERATOR-END: IcedConstants

3
src/rust/iced-x86/src/info/cpuid_table.rs
View File

@ -26,7 +26,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
use super::super::CpuidFeature;
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(crate) static CPUID: [&[CpuidFeature]; 175] = [
pub(crate) static CPUID: [&[CpuidFeature]; 176] = [
&[CpuidFeature::INTEL8086],// INTEL8086
&[CpuidFeature::INTEL8086_ONLY],// INTEL8086_ONLY
&[CpuidFeature::INTEL186],// INTEL186
@ -202,4 +202,5 @@ pub(crate) static CPUID: [&[CpuidFeature]; 175] = [
&[CpuidFeature::UINTR],// UINTR
&[CpuidFeature::HRESET],// HRESET
&[CpuidFeature::AVX_VNNI],// AVX_VNNI
&[CpuidFeature::PADLOCK_GMI],// PADLOCK_GMI
];

42
src/rust/iced-x86/src/info/enums.rs
View File

@ -440,9 +440,9 @@ pub(crate) enum ImpliedAccess {
t_CRmem_CRsi_CReax_CRes_CWeax_CWedx_RCWecx,
t_CRmem_CReax_CResi_CRes_CWeax_CWedx_RCWecx,
t_CRmem_CReax_CRrsi_CRes_CWeax_CWedx_RCWrcx,
t_CRmem_CRmem_CWmem_CRax_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CWmem_CReax_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CWmem_CRrax_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx,
t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx,
t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx,
t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx,
t_Rcl_Rax,
t_Rcl_Reax,
t_xstore2,
@ -451,9 +451,9 @@ pub(crate) enum ImpliedAccess {
t_CRmem_CRmem_CRmem_CWmem_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CRmem_CWmem_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CRmem_CWmem_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
t_RCWal,
t_RCWax,
t_RCWeax,
@ -499,10 +499,16 @@ pub(crate) enum ImpliedAccess {
t_Wxmm1_Wxmm2_RWxmm0_Wxmm4TOxmm6,
t_RWxmm0_RWxmm1_Wxmm2TOxmm6,
t_pop3x8,
t_CRmem_CRmem_CWmem_CRbx_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx,
t_CRmem_CRmem_CWmem_CRebx_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx,
t_CRmem_CRmem_CWmem_CRrbx_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx,
t_CRmem_CRmem_CWmem_CRax_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx,
t_CRmem_CRmem_CWmem_CReax_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx,
t_CRmem_CRmem_CWmem_CRrax_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_IMPLIED_ACCESS: [&str; 182] = [
static GEN_DEBUG_IMPLIED_ACCESS: [&str; 188] = [
"None",
"Shift_Ib_MASK1FMOD9",
"Shift_Ib_MASK1FMOD11",
@ -626,9 +632,9 @@ static GEN_DEBUG_IMPLIED_ACCESS: [&str; 182] = [
"t_CRmem_CRsi_CReax_CRes_CWeax_CWedx_RCWecx",
"t_CRmem_CReax_CResi_CRes_CWeax_CWedx_RCWecx",
"t_CRmem_CReax_CRrsi_CRes_CWeax_CWedx_RCWrcx",
"t_CRmem_CRmem_CWmem_CRax_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx",
"t_CRmem_CRmem_CWmem_CReax_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx",
"t_CRmem_CRmem_CWmem_CRrax_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx",
"t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx",
"t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx",
"t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx",
"t_Rcl_Rax",
"t_Rcl_Reax",
"t_xstore2",
@ -637,9 +643,9 @@ static GEN_DEBUG_IMPLIED_ACCESS: [&str; 182] = [
"t_CRmem_CRmem_CRmem_CWmem_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx",
"t_CRmem_CRmem_CRmem_CWmem_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx",
"t_CRmem_CRmem_CRmem_CWmem_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx",
"t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx",
"t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx",
"t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx",
"t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx",
"t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx",
"t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx",
"t_RCWal",
"t_RCWax",
"t_RCWeax",
@ -685,6 +691,12 @@ static GEN_DEBUG_IMPLIED_ACCESS: [&str; 182] = [
"t_Wxmm1_Wxmm2_RWxmm0_Wxmm4TOxmm6",
"t_RWxmm0_RWxmm1_Wxmm2TOxmm6",
"t_pop3x8",
"t_CRmem_CRmem_CWmem_CRbx_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx",
"t_CRmem_CRmem_CWmem_CRebx_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx",
"t_CRmem_CRmem_CWmem_CRrbx_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx",
"t_CRmem_CRmem_CWmem_CRax_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx",
"t_CRmem_CRmem_CWmem_CReax_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx",
"t_CRmem_CRmem_CWmem_CRrax_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for ImpliedAccess {
@ -1074,10 +1086,11 @@ pub(crate) enum CpuidFeatureInternal {
UINTR,
HRESET,
AVX_VNNI,
PADLOCK_GMI,
}
#[cfg(feature = "instr_info")]
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_CPUID_FEATURE_INTERNAL: [&str; 175] = [
static GEN_DEBUG_CPUID_FEATURE_INTERNAL: [&str; 176] = [
"INTEL8086",
"INTEL8086_ONLY",
"INTEL186",
@ -1253,6 +1266,7 @@ static GEN_DEBUG_CPUID_FEATURE_INTERNAL: [&str; 175] = [
"UINTR",
"HRESET",
"AVX_VNNI",
"PADLOCK_GMI",
];
#[cfg(feature = "instr_info")]
impl fmt::Debug for CpuidFeatureInternal {

138
src/rust/iced-x86/src/info/factory.rs
View File

@ -1258,60 +1258,54 @@ impl InstructionInfoFactory {
Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRax_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx => {
ImpliedAccess::t_CRmem_CRmem_CWmem_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::SI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code16, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::AX, OpAccess::CondRead);
Self::add_register(flags, info, Register::SI, OpAccess::CondRead);
Self::add_register(flags, info, Register::DI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::AX, OpAccess::CondWrite);
Self::add_register(flags, info, Register::SI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::DI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::AX, OpAccess::ReadCondWrite);
Self::add_register(flags, info, Register::CX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CReax_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx => {
ImpliedAccess::t_CRmem_CRmem_CWmem_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::ESI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code32, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::EAX, OpAccess::CondRead);
Self::add_register(flags, info, Register::ESI, OpAccess::CondRead);
Self::add_register(flags, info, Register::EDI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::EAX, OpAccess::CondWrite);
Self::add_register(flags, info, Register::ESI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::EDI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::EAX, OpAccess::ReadCondWrite);
Self::add_register(flags, info, Register::ECX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRrax_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx => {
ImpliedAccess::t_CRmem_CRmem_CWmem_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::RSI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code64, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::RAX, OpAccess::CondRead);
Self::add_register(flags, info, Register::RSI, OpAccess::CondRead);
Self::add_register(flags, info, Register::RDI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::RAX, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RSI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RDI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RAX, OpAccess::ReadCondWrite);
Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite);
}
}
@ -1396,7 +1390,7 @@ impl InstructionInfoFactory {
Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWax_CWsi_CWdi_RCWcx => {
ImpliedAccess::t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRax_CRdx_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::AX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::DX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
@ -1414,13 +1408,12 @@ impl InstructionInfoFactory {
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::AX, OpAccess::CondWrite);
Self::add_register(flags, info, Register::SI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::DI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::CX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWeax_CWesi_CWedi_RCWecx => {
ImpliedAccess::t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CReax_CRedx_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::EAX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::EDX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
@ -1438,13 +1431,12 @@ impl InstructionInfoFactory {
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::EAX, OpAccess::CondWrite);
Self::add_register(flags, info, Register::ESI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::EDI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::ECX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrax_CWrsi_CWrdi_RCWrcx => {
ImpliedAccess::t_CRmem_CRmem_CRmem_CRmem_CWmem_CWmem_CRrax_CRrdx_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::RAX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RDX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
@ -1462,7 +1454,6 @@ impl InstructionInfoFactory {
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::RAX, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RSI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RDI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite);
@ -1755,6 +1746,117 @@ impl InstructionInfoFactory {
ImpliedAccess::t_pop3x8 => {
Self::command_pop(instruction, info, flags, 3, 8);
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRbx_CRsi_CRdi_CRes_CWsi_RCWax_RCWcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::SI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code16, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::BX, OpAccess::CondRead);
Self::add_register(flags, info, Register::SI, OpAccess::CondRead);
Self::add_register(flags, info, Register::DI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::SI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::AX, OpAccess::ReadCondWrite);
Self::add_register(flags, info, Register::CX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRebx_CResi_CRedi_CRes_CWesi_RCWeax_RCWecx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::ESI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code32, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::EBX, OpAccess::CondRead);
Self::add_register(flags, info, Register::ESI, OpAccess::CondRead);
Self::add_register(flags, info, Register::EDI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::ESI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::EAX, OpAccess::ReadCondWrite);
Self::add_register(flags, info, Register::ECX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRrbx_CRrsi_CRrdi_CRes_CWrsi_RCWrax_RCWrcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::RSI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code64, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::RBX, OpAccess::CondRead);
Self::add_register(flags, info, Register::RSI, OpAccess::CondRead);
Self::add_register(flags, info, Register::RDI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::RSI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RAX, OpAccess::ReadCondWrite);
Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRax_CRbx_CRsi_CRdi_CRes_CWsi_CWdi_RCWcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::BX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::SI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code16, 0);
Self::add_memory(info, Register::ES, Register::DI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code16, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::AX, OpAccess::CondRead);
Self::add_register(flags, info, Register::BX, OpAccess::CondRead);
Self::add_register(flags, info, Register::SI, OpAccess::CondRead);
Self::add_register(flags, info, Register::DI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::SI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::DI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::CX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CReax_CRebx_CResi_CRedi_CRes_CWesi_CWedi_RCWecx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::EBX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::ESI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code32, 0);
Self::add_memory(info, Register::ES, Register::EDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code32, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::EAX, OpAccess::CondRead);
Self::add_register(flags, info, Register::EBX, OpAccess::CondRead);
Self::add_register(flags, info, Register::ESI, OpAccess::CondRead);
Self::add_register(flags, info, Register::EDI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::ESI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::EDI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::ECX, OpAccess::ReadCondWrite);
}
}
ImpliedAccess::t_CRmem_CRmem_CWmem_CRrax_CRrbx_CRrsi_CRrdi_CRes_CWrsi_CWrdi_RCWrcx => {
if (flags & Flags::NO_MEMORY_USAGE) == 0 {
Self::add_memory(info, Register::ES, Register::RBX, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RSI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondRead, CodeSize::Code64, 0);
Self::add_memory(info, Register::ES, Register::RDI, Register::None, 1, 0x0, MemorySize::Unknown, OpAccess::CondWrite, CodeSize::Code64, 0);
}
if (flags & Flags::NO_REGISTER_USAGE) == 0 {
Self::add_register(flags, info, Register::RAX, OpAccess::CondRead);
Self::add_register(flags, info, Register::RBX, OpAccess::CondRead);
Self::add_register(flags, info, Register::RSI, OpAccess::CondRead);
Self::add_register(flags, info, Register::RDI, OpAccess::CondRead);
if (flags & Flags::IS_64BIT) == 0 {
Self::add_register(flags, info, Register::ES, OpAccess::CondRead);
}
Self::add_register(flags, info, Register::RSI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RDI, OpAccess::CondWrite);
Self::add_register(flags, info, Register::RCX, OpAccess::ReadCondWrite);
}
}
// GENERATOR-END: ImpliedAccessHandler
}
}

8
src/rust/iced-x86/src/info/info_table.rs
View File

@ -24,7 +24,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ⚠️This file was generated by GENERATOR!🦹‍♂️
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
pub(crate) static TABLE: [u32; 8624] = [
pub(crate) static TABLE: [u32; 8636] = [
0x0000_0000, 0x0090_0000,// INVALID
0x0000_0000, 0x0090_0000,// DeclareByte
0x0000_0000, 0x0090_0000,// DeclareWord
@ -4337,4 +4337,10 @@ pub(crate) static TABLE: [u32; 8624] = [
0x0000_00B6, 0xAE00_0001,// VEX_Vpdpwssd_ymm_ymm_ymmm256
0x0000_00B6, 0xAE00_0001,// VEX_Vpdpwssds_xmm_xmm_xmmm128
0x0000_00B6, 0xAE00_0001,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0x0B60_0000, 0xAF00_0000,// Ccs_hash_16
0x0B70_0000, 0xAF00_0000,// Ccs_hash_32
0x0B80_0000, 0xAF00_0000,// Ccs_hash_64
0x0B90_0000, 0xAF00_0000,// Ccs_encrypt_16
0x0BA0_0000, 0xAF00_0000,// Ccs_encrypt_32
0x0BB0_0000, 0xAF00_0000,// Ccs_encrypt_64
];

12
src/rust/iced-x86/src/instruction_memory_sizes.rs
View File

@ -4342,6 +4342,12 @@ pub(super) static SIZES: [MemorySize; IcedConstants::NUMBER_OF_CODE_VALUES * 2]
MemorySize::Packed256_Int16,// VEX_Vpdpwssd_ymm_ymm_ymmm256
MemorySize::Packed128_Int16,// VEX_Vpdpwssds_xmm_xmm_xmmm128
MemorySize::Packed256_Int16,// VEX_Vpdpwssds_ymm_ymm_ymmm256
MemorySize::Unknown,// Ccs_hash_16
MemorySize::Unknown,// Ccs_hash_32
MemorySize::Unknown,// Ccs_hash_64
MemorySize::Unknown,// Ccs_encrypt_16
MemorySize::Unknown,// Ccs_encrypt_32
MemorySize::Unknown,// Ccs_encrypt_64
MemorySize::Unknown,// INVALID
MemorySize::Unknown,// DeclareByte
MemorySize::Unknown,// DeclareWord
@ -8654,4 +8660,10 @@ pub(super) static SIZES: [MemorySize; IcedConstants::NUMBER_OF_CODE_VALUES * 2]
MemorySize::Unknown,// VEX_Vpdpwssd_ymm_ymm_ymmm256
MemorySize::Unknown,// VEX_Vpdpwssds_xmm_xmm_xmmm128
MemorySize::Unknown,// VEX_Vpdpwssds_ymm_ymm_ymmm256
MemorySize::Unknown,// Ccs_hash_16
MemorySize::Unknown,// Ccs_hash_32
MemorySize::Unknown,// Ccs_hash_64
MemorySize::Unknown,// Ccs_encrypt_16
MemorySize::Unknown,// Ccs_encrypt_32
MemorySize::Unknown,// Ccs_encrypt_64
];

6
src/rust/iced-x86/src/instruction_op_counts.rs
View File

@ -4339,4 +4339,10 @@ pub(super) static OP_COUNT: [u8; IcedConstants::NUMBER_OF_CODE_VALUES] = [
3,// VEX_Vpdpwssd_ymm_ymm_ymmm256
3,// VEX_Vpdpwssds_xmm_xmm_xmmm128
3,// VEX_Vpdpwssds_ymm_ymm_ymmm256
0,// Ccs_hash_16
0,// Ccs_hash_32
0,// Ccs_hash_64
0,// Ccs_encrypt_16
0,// Ccs_encrypt_32
0,// Ccs_encrypt_64
];

6
src/rust/iced-x86/src/mnemonic.rs
View File

@ -1658,9 +1658,11 @@ pub enum Mnemonic {
Stui = 1624,
Senduipi = 1625,
Hreset = 1626,
Ccs_hash = 1627,
Ccs_encrypt = 1628,
}
#[cfg_attr(feature = "cargo-fmt", rustfmt::skip)]
static GEN_DEBUG_MNEMONIC: [&str; 1627] = [
static GEN_DEBUG_MNEMONIC: [&str; 1629] = [
"INVALID",
"Aaa",
"Aad",
@ -3288,6 +3290,8 @@ static GEN_DEBUG_MNEMONIC: [&str; 1627] = [
"Stui",
"Senduipi",
"Hreset",
"Ccs_hash",
"Ccs_encrypt",
];
impl fmt::Debug for Mnemonic {
#[inline]

6
src/rust/iced-x86/src/mnemonics.rs
View File

@ -4340,4 +4340,10 @@ pub(super) static TO_MNEMONIC: [Mnemonic; IcedConstants::NUMBER_OF_CODE_VALUES]
Mnemonic::Vpdpwssd,// VEX_Vpdpwssd_ymm_ymm_ymmm256
Mnemonic::Vpdpwssds,// VEX_Vpdpwssds_xmm_xmm_xmmm128
Mnemonic::Vpdpwssds,// VEX_Vpdpwssds_ymm_ymm_ymmm256
Mnemonic::Ccs_hash,// Ccs_hash_16
Mnemonic::Ccs_hash,// Ccs_hash_32
Mnemonic::Ccs_hash,// Ccs_hash_64
Mnemonic::Ccs_encrypt,// Ccs_encrypt_16
Mnemonic::Ccs_encrypt,// Ccs_encrypt_32
Mnemonic::Ccs_encrypt,// Ccs_encrypt_64
];

8
src/rust/iced-x86/src/test_utils/from_str_conv/code_table.rs
View File

@ -33,7 +33,7 @@ lazy_static! {
pub(super) static ref TO_CODE_HASH: HashMap<&'static str, Code> = {
// GENERATOR-BEGIN: CodeHash
// ⚠️This was generated by GENERATOR!🦹‍♂️
let mut h = HashMap::with_capacity(4312);
let mut h = HashMap::with_capacity(4318);
h.insert("INVALID", Code::INVALID);
h.insert("DeclareByte", Code::DeclareByte);
h.insert("DeclareWord", Code::DeclareWord);
@ -4346,6 +4346,12 @@ lazy_static! {
h.insert("VEX_Vpdpwssd_ymm_ymm_ymmm256", Code::VEX_Vpdpwssd_ymm_ymm_ymmm256);
h.insert("VEX_Vpdpwssds_xmm_xmm_xmmm128", Code::VEX_Vpdpwssds_xmm_xmm_xmmm128);
h.insert("VEX_Vpdpwssds_ymm_ymm_ymmm256", Code::VEX_Vpdpwssds_ymm_ymm_ymmm256);
h.insert("Ccs_hash_16", Code::Ccs_hash_16);
h.insert("Ccs_hash_32", Code::Ccs_hash_32);
h.insert("Ccs_hash_64", Code::Ccs_hash_64);
h.insert("Ccs_encrypt_16", Code::Ccs_encrypt_16);
h.insert("Ccs_encrypt_32", Code::Ccs_encrypt_32);
h.insert("Ccs_encrypt_64", Code::Ccs_encrypt_64);
// GENERATOR-END: CodeHash
h
};

Some files were not shown because too many files have changed in this diff Show More