1716 Commits

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Author	SHA1	Message	Date
0xd4d	6e9f598cc5	Verify smm/sgx/vmx/seam flags	2020-10-18 16:17:18 +02:00
0xd4d	aa78af0339	Add OpCodeInfo::op_kinds()	2020-10-18 16:17:10 +02:00
0xd4d	3d57bcab5f	Update defs, some only read lower 8/16 bits of regs	2020-10-18 16:17:02 +02:00
0xd4d	4b8ab2ffad	Create implied accesses enum after instrs have been filtered	2020-10-17 11:31:42 +02:00
0xd4d	e7e9a6cb66	Move emmi enum code to the base class	2020-10-17 11:31:26 +02:00
0xd4d	69c8a84d2b	Remove K0 static assert	2020-10-15 20:44:28 +02:00
0xd4d	8b1919e7c2	Get rid of Code enum ref by adding an arg to xstore=xxx	2020-10-15 20:44:20 +02:00
0xd4d	ee38014613	Add Get*Filename() methods	2020-10-15 20:44:11 +02:00
0xd4d	7f48a5a192	Add Static.Assert to generator	2020-10-15 20:44:03 +02:00
0xd4d	7b51ae6d45	Return a tuple, remove out arg	2020-10-15 20:43:55 +02:00
0xd4d	14ddebfadf	Remove some static asserts	2020-10-15 20:43:48 +02:00
0xd4d	de63b9a51c	Disable unreadable_literal	2020-10-15 00:58:04 +02:00
0xd4d	9b1ecdf968	Move funcs to base	2020-10-15 00:35:37 +02:00
0xd4d	7e00e5b7f4	Generate implied reg/mem accesses switch table	2020-10-15 00:26:37 +02:00
0xd4d	258163b16e	Generate the code that prints the implied ops	2020-10-13 19:49:08 +02:00
0xd4d	780b8d2c5a	Add MustBeCpl0 prop	2020-10-13 19:49:00 +02:00
0xd4d	0a62491e71	Use correct fmt line index and use switch expr	2020-10-13 19:48:52 +02:00
0xd4d	7aee5a4290	Remove r64 encoding	2020-10-13 19:48:44 +02:00
0xd4d	ef39d61b37	Add no-in-sgx flag	2020-10-13 19:48:18 +02:00
0xd4d	09e332cc8a	rustfmt	2020-10-11 19:05:24 +02:00
0xd4d	d7d4f3757f	REX.W -> o64	2020-10-11 18:35:08 +02:00
0xd4d	928eaa2d5b	Remove unused code	2020-10-11 12:55:53 +02:00
0xd4d	9f5d010d8e	Use a better error message if REX.W is used instead of o64	2020-10-11 12:55:46 +02:00
0xd4d	e885b6db78	Add new Intel instructions: UINTR, HRESET, AVX_VNNI	2020-10-11 03:51:10 +02:00
0xd4d	c744c835c2	Add opsize=64 to instrs with default opsize=64	2020-10-10 15:00:55 +02:00
0xd4d	44e3b7fb3c	Verify size index	2020-10-10 12:29:05 +02:00
0xd4d	cbe3000962	Don't use default(FormatterString)	2020-10-10 12:24:16 +02:00
0xd4d	9747caf12a	Generate more stuff	2020-10-10 11:51:09 +02:00
0xd4d	4cb8b352d2	Move reg defs to a text file	2020-10-09 17:33:06 +02:00
0xd4d	2dd9c2e881	Update reg16/32 fmt handlers	2020-10-09 17:32:58 +02:00
0xd4d	6cd00f6a8e	Sort the instr defs	2020-10-09 17:32:52 +02:00
0xd4d	d1b52cd6d9	Generate test txt files	2020-10-09 17:32:45 +02:00
0xd4d	9983d52877	ForceReservednop -> ForceReservedNop	2020-10-09 17:32:36 +02:00
0xd4d	63c40cdb0a	Update AssemblerTestBase to use the new OpCodeInfo props	2020-10-09 17:32:29 +02:00
0xd4d	298fea948e	Add opcode checks, rename an enum field	2020-10-09 17:32:22 +02:00
0xd4d	16b4f0b7c9	Update OpCodeInfos.txt	2020-10-09 01:12:51 +02:00
0xd4d	3cce636f7c	Remove 1.45 bug workaround, add more js tests, fix warnings/errors	2020-10-08 23:31:28 +02:00
0xd4d	0b07962a9f	Add r64 Code values too	2020-10-08 21:47:19 +02:00
0xd4d	0aade6dcd8	Add new OpCodeInfo props using the new flags	2020-10-08 21:47:13 +02:00
0xd4d	e415c73f9d	Refactor encoder/opcode info tables, add the new flags	2020-10-07 22:44:28 +02:00
0xd4d	40415a04eb	Update instruction defs, add more flags	2020-10-06 19:44:16 +02:00
0xd4d	952108963b	Add jmpe to BranchKind	2020-10-06 19:44:06 +02:00
0xd4d	1a8b9f637f	Move instruction defs to a text file, some other refactorings too	2020-09-29 22:32:04 +02:00
0xd4d	22531a1080	Update README	2020-09-24 19:36:40 +02:00
0xd4d	e484b58bd4	Rename some more	2020-09-20 21:24:50 +02:00
0xd4d	7b72838643	Refactor fmt handlers	2020-09-20 02:31:29 +02:00
0xd4d	e94a776d26	nasm: don't ignore mem size	2020-09-19 23:23:15 +02:00
0xd4d	78ce14b541	Don't show mem size if movsxd and fast/intel/nasm	2020-09-19 21:56:46 +02:00
0xd4d	d505394152	Update instr def table	2020-09-18 16:44:05 +02:00
0xd4d	d7b5e46c13	Change Int3 instr mnemonic from Int to Int3	2020-09-18 15:50:17 +02:00