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Remove old deprecated code

This commit is contained in:
wtfsck 2021-01-26 17:55:15 +01:00
parent 820ab741a9
commit 491caf22e0
6 changed files with 0 additions and 53 deletions
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4
src/csharp/Intel/Generator/Enums/Decoder/DecoderOptions.cs
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@ -11,8 +11,6 @@ namespace Generator.Enums.Decoder {
NoInvalidCheck = 0x00000001, NoInvalidCheck = 0x00000001,
[Comment("AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no #(c:o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS)#, #(c:UD0)# has no modr/m byte, decode #(c:LOCK MOV CR)#. The AMD decoder can still decode Intel instructions.")] [Comment("AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no #(c:o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS)#, #(c:UD0)# has no modr/m byte, decode #(c:LOCK MOV CR)#. The AMD decoder can still decode Intel instructions.")]
AMD = 0x00000002, AMD = 0x00000002,
[Deprecated("1.8.0", nameof(AMD))]
AmdBranches,
[Comment("Decode opcodes #(c:0F0D)# and #(c:0F18-0F1F)# as reserved-nop instructions (eg. #(e:Code.Reservednop_rm32_r32_0F1D)#)")] [Comment("Decode opcodes #(c:0F0D)# and #(c:0F18-0F1F)# as reserved-nop instructions (eg. #(e:Code.Reservednop_rm32_r32_0F1D)#)")]
ForceReservedNop = 0x00000004, ForceReservedNop = 0x00000004,
[Comment("Decode #(c:UMOV)# instructions")] [Comment("Decode #(c:UMOV)# instructions")]
@ -42,8 +40,6 @@ namespace Generator.Enums.Decoder {
[Comment("Don't decode #(c:LOCK MOV CR0)# as #(c:MOV CR8)# (AMD)")] [Comment("Don't decode #(c:LOCK MOV CR0)# as #(c:MOV CR8)# (AMD)")]
[Deprecated("1.11.0", null, "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")] [Deprecated("1.11.0", null, "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")]
NoLockMovCR = 0x00008000, NoLockMovCR = 0x00008000,
[Deprecated("1.9.0", nameof(NoLockMovCR), "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")]
NoLockMovCR0,
[Comment("Don't decode #(c:TZCNT)#, decode #(c:BSF)# instead")] [Comment("Don't decode #(c:TZCNT)#, decode #(c:BSF)# instead")]
NoMPFX_0FBC = 0x00010000, NoMPFX_0FBC = 0x00010000,
[Comment("Don't decode #(c:LZCNT)#, decode #(c:BSR)# instead")] [Comment("Don't decode #(c:LZCNT)#, decode #(c:BSR)# instead")]

8
src/csharp/Intel/Iced/Intel/Decoder.cs
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@ -247,14 +247,6 @@ namespace Iced.Intel {
[MethodImpl(MethodImplOptions.AggressiveInlining)] [MethodImpl(MethodImplOptions.AggressiveInlining)]
internal uint ReadUInt32() => ReadByte() | (ReadByte() << 8) | (ReadByte() << 16) | (ReadByte() << 24); internal uint ReadUInt32() => ReadByte() | (ReadByte() << 8) | (ReadByte() << 16) | (ReadByte() << 24);
/// <summary>
/// This property can be tested after calling <see cref="Decode()"/> and <see cref="Decode(out Instruction)"/>
/// to check if the decoded instruction is invalid because there's no more bytes left or because of bad input data.
/// </summary>
[System.Obsolete("Use " + nameof(LastError) + " instead", true)]
[System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)]
public bool InvalidNoMoreBytes => (state.flags & StateFlags.NoMoreBytes) != 0;
/// <summary> /// <summary>
/// Gets the last decoder error. Unless you need to know the reason it failed, /// Gets the last decoder error. Unless you need to know the reason it failed,
/// it's better to check <see cref="Instruction.IsInvalid"/>. /// it's better to check <see cref="Instruction.IsInvalid"/>.

8
src/csharp/Intel/Iced/Intel/DecoderOptions.g.cs
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@ -19,10 +19,6 @@ namespace Iced.Intel {
NoInvalidCheck = 0x00000001, NoInvalidCheck = 0x00000001,
/// <summary>AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no <c>o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS</c>, <c>UD0</c> has no modr/m byte, decode <c>LOCK MOV CR</c>. The AMD decoder can still decode Intel instructions.</summary> /// <summary>AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no <c>o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS</c>, <c>UD0</c> has no modr/m byte, decode <c>LOCK MOV CR</c>. The AMD decoder can still decode Intel instructions.</summary>
AMD = 0x00000002, AMD = 0x00000002,
/// <summary>AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no <c>o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS</c>, <c>UD0</c> has no modr/m byte, decode <c>LOCK MOV CR</c>. The AMD decoder can still decode Intel instructions.</summary>
[System.Obsolete("Use " + nameof(AMD) + " instead", true)]
[System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)]
AmdBranches = 0x00000002,
/// <summary>Decode opcodes <c>0F0D</c> and <c>0F18-0F1F</c> as reserved-nop instructions (eg. <see cref="Code.Reservednop_rm32_r32_0F1D"/>)</summary> /// <summary>Decode opcodes <c>0F0D</c> and <c>0F18-0F1F</c> as reserved-nop instructions (eg. <see cref="Code.Reservednop_rm32_r32_0F1D"/>)</summary>
ForceReservedNop = 0x00000004, ForceReservedNop = 0x00000004,
/// <summary>Decode <c>UMOV</c> instructions</summary> /// <summary>Decode <c>UMOV</c> instructions</summary>
@ -53,10 +49,6 @@ namespace Iced.Intel {
[System.Obsolete("This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.", true)] [System.Obsolete("This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.", true)]
[System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)] [System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)]
NoLockMovCR = 0x00008000, NoLockMovCR = 0x00008000,
/// <summary>Don&apos;t decode <c>LOCK MOV CR0</c> as <c>MOV CR8</c> (AMD)</summary>
[System.Obsolete("This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.", true)]
[System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)]
NoLockMovCR0 = 0x00008000,
/// <summary>Don&apos;t decode <c>TZCNT</c>, decode <c>BSF</c> instead</summary> /// <summary>Don&apos;t decode <c>TZCNT</c>, decode <c>BSF</c> instead</summary>
NoMPFX_0FBC = 0x00010000, NoMPFX_0FBC = 0x00010000,
/// <summary>Don&apos;t decode <c>LZCNT</c>, decode <c>BSR</c> instead</summary> /// <summary>Don&apos;t decode <c>LZCNT</c>, decode <c>BSR</c> instead</summary>

7
src/csharp/Intel/Iced/Intel/OpCodeInfo.cs
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@ -380,13 +380,6 @@ namespace Iced.Intel {
/// </summary> /// </summary>
public bool RequireOpMaskRegister => (encFlags3 & EncFlags3.RequireOpMaskRegister) != 0; public bool RequireOpMaskRegister => (encFlags3 & EncFlags3.RequireOpMaskRegister) != 0;
/// <summary>
/// (EVEX) <see langword="true"/> if a non-zero opmask register must be used
/// </summary>
[System.Obsolete("Use " + nameof(RequireOpMaskRegister) + " instead", true)]
[System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)]
public bool RequireNonZeroOpMaskRegister => RequireOpMaskRegister;
/// <summary> /// <summary>
/// (EVEX) <see langword="true"/> if the instruction supports zeroing masking (if one of the opmask registers <c>K1</c>-<c>K7</c> is used and destination operand is not a memory operand) /// (EVEX) <see langword="true"/> if the instruction supports zeroing masking (if one of the opmask registers <c>K1</c>-<c>K7</c> is used and destination operand is not a memory operand)
/// </summary> /// </summary>

18
src/rust/iced-x86/src/decoder.rs
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@ -121,9 +121,6 @@ impl DecoderOptions {
pub const NO_INVALID_CHECK: u32 = 0x0000_0001; pub const NO_INVALID_CHECK: u32 = 0x0000_0001;
/// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no `o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS`, `UD0` has no modr/m byte, decode `LOCK MOV CR`. The AMD decoder can still decode Intel instructions. /// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no `o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS`, `UD0` has no modr/m byte, decode `LOCK MOV CR`. The AMD decoder can still decode Intel instructions.
pub const AMD: u32 = 0x0000_0002; pub const AMD: u32 = 0x0000_0002;
/// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no `o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS`, `UD0` has no modr/m byte, decode `LOCK MOV CR`. The AMD decoder can still decode Intel instructions.
#[deprecated(since = "1.8.0", note = "Use AMD instead")]
pub const AMD_BRANCHES: u32 = 0x0000_0002;
/// Decode opcodes `0F0D` and `0F18-0F1F` as reserved-nop instructions (eg. [`Code::Reservednop_rm32_r32_0F1D`]) /// Decode opcodes `0F0D` and `0F18-0F1F` as reserved-nop instructions (eg. [`Code::Reservednop_rm32_r32_0F1D`])
/// ///
/// [`Code::Reservednop_rm32_r32_0F1D`]: enum.Code.html#variant.Reservednop_rm32_r32_0F1D /// [`Code::Reservednop_rm32_r32_0F1D`]: enum.Code.html#variant.Reservednop_rm32_r32_0F1D
@ -155,9 +152,6 @@ impl DecoderOptions {
/// Don't decode `LOCK MOV CR0` as `MOV CR8` (AMD) /// Don't decode `LOCK MOV CR0` as `MOV CR8` (AMD)
#[deprecated(since = "1.11.0", note = "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")] #[deprecated(since = "1.11.0", note = "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")]
pub const NO_LOCK_MOV_CR: u32 = 0x0000_8000; pub const NO_LOCK_MOV_CR: u32 = 0x0000_8000;
/// Don't decode `LOCK MOV CR0` as `MOV CR8` (AMD)
#[deprecated(since = "1.9.0", note = "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")]
pub const NO_LOCK_MOV_CR0: u32 = 0x0000_8000;
/// Don't decode `TZCNT`, decode `BSF` instead /// Don't decode `TZCNT`, decode `BSF` instead
pub const NO_MPFX_0FBC: u32 = 0x0001_0000; pub const NO_MPFX_0FBC: u32 = 0x0001_0000;
/// Don't decode `LZCNT`, decode `BSR` instead /// Don't decode `LZCNT`, decode `BSR` instead
@ -862,18 +856,6 @@ impl<'a> Decoder<'a> {
mk_read_value! {self, u32, u32::from_le} mk_read_value! {self, u32, u32::from_le}
} }
/// This method can be called after calling [`decode()`] and [`decode_out()`] to check if the
/// decoded instruction is invalid because there's no more bytes left or because of bad input data.
///
/// [`decode()`]: #method.decode
/// [`decode_out()`]: #method.decode_out
#[must_use]
#[inline]
#[deprecated(since = "1.8.0", note = "Use last_error() instead")]
pub fn invalid_no_more_bytes(&self) -> bool {
(self.state.flags & StateFlags::NO_MORE_BYTES) != 0
}
/// Gets the last decoder error. Unless you need to know the reason it failed, /// Gets the last decoder error. Unless you need to know the reason it failed,
/// it's better to check [`instruction.is_invalid()`]. /// it's better to check [`instruction.is_invalid()`].
/// ///

8
src/rust/iced-x86/src/encoder/op_code.rs
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@ -557,14 +557,6 @@ impl OpCodeInfo {
(self.enc_flags3 & EncFlags3::REQUIRE_OP_MASK_REGISTER) != 0 (self.enc_flags3 & EncFlags3::REQUIRE_OP_MASK_REGISTER) != 0
} }
/// (EVEX) `true` if a non-zero op mask register must be used
#[deprecated(since = "1.9.0", note = "Use require_op_mask_register() instead")]
#[must_use]
#[inline]
pub fn require_non_zero_op_mask_register(&self) -> bool {
self.require_op_mask_register()
}
/// (EVEX) `true` if the instruction supports zeroing masking (if one of the op mask registers `K1`-`K7` is used and destination operand is not a memory operand) /// (EVEX) `true` if the instruction supports zeroing masking (if one of the op mask registers `K1`-`K7` is used and destination operand is not a memory operand)
#[must_use] #[must_use]
#[inline] #[inline]