diff --git a/src/csharp/Intel/Generator/Enums/Decoder/DecoderOptions.cs b/src/csharp/Intel/Generator/Enums/Decoder/DecoderOptions.cs index a6c478440..80370c9f3 100644 --- a/src/csharp/Intel/Generator/Enums/Decoder/DecoderOptions.cs +++ b/src/csharp/Intel/Generator/Enums/Decoder/DecoderOptions.cs @@ -11,8 +11,6 @@ namespace Generator.Enums.Decoder { NoInvalidCheck = 0x00000001, [Comment("AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no #(c:o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS)#, #(c:UD0)# has no modr/m byte, decode #(c:LOCK MOV CR)#. The AMD decoder can still decode Intel instructions.")] AMD = 0x00000002, - [Deprecated("1.8.0", nameof(AMD))] - AmdBranches, [Comment("Decode opcodes #(c:0F0D)# and #(c:0F18-0F1F)# as reserved-nop instructions (eg. #(e:Code.Reservednop_rm32_r32_0F1D)#)")] ForceReservedNop = 0x00000004, [Comment("Decode #(c:UMOV)# instructions")] @@ -42,8 +40,6 @@ namespace Generator.Enums.Decoder { [Comment("Don't decode #(c:LOCK MOV CR0)# as #(c:MOV CR8)# (AMD)")] [Deprecated("1.11.0", null, "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")] NoLockMovCR = 0x00008000, - [Deprecated("1.9.0", nameof(NoLockMovCR), "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")] - NoLockMovCR0, [Comment("Don't decode #(c:TZCNT)#, decode #(c:BSF)# instead")] NoMPFX_0FBC = 0x00010000, [Comment("Don't decode #(c:LZCNT)#, decode #(c:BSR)# instead")] diff --git a/src/csharp/Intel/Iced/Intel/Decoder.cs b/src/csharp/Intel/Iced/Intel/Decoder.cs index 9ae868085..e7fd9dedf 100644 --- a/src/csharp/Intel/Iced/Intel/Decoder.cs +++ b/src/csharp/Intel/Iced/Intel/Decoder.cs @@ -247,14 +247,6 @@ namespace Iced.Intel { [MethodImpl(MethodImplOptions.AggressiveInlining)] internal uint ReadUInt32() => ReadByte() | (ReadByte() << 8) | (ReadByte() << 16) | (ReadByte() << 24); - /// - /// This property can be tested after calling and - /// to check if the decoded instruction is invalid because there's no more bytes left or because of bad input data. - /// - [System.Obsolete("Use " + nameof(LastError) + " instead", true)] - [System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)] - public bool InvalidNoMoreBytes => (state.flags & StateFlags.NoMoreBytes) != 0; - /// /// Gets the last decoder error. Unless you need to know the reason it failed, /// it's better to check . diff --git a/src/csharp/Intel/Iced/Intel/DecoderOptions.g.cs b/src/csharp/Intel/Iced/Intel/DecoderOptions.g.cs index 9729dffdc..f7e5f0c09 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderOptions.g.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderOptions.g.cs @@ -19,10 +19,6 @@ namespace Iced.Intel { NoInvalidCheck = 0x00000001, /// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS, UD0 has no modr/m byte, decode LOCK MOV CR. The AMD decoder can still decode Intel instructions. AMD = 0x00000002, - /// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS, UD0 has no modr/m byte, decode LOCK MOV CR. The AMD decoder can still decode Intel instructions. - [System.Obsolete("Use " + nameof(AMD) + " instead", true)] - [System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)] - AmdBranches = 0x00000002, /// Decode opcodes 0F0D and 0F18-0F1F as reserved-nop instructions (eg. ) ForceReservedNop = 0x00000004, /// Decode UMOV instructions @@ -53,10 +49,6 @@ namespace Iced.Intel { [System.Obsolete("This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.", true)] [System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)] NoLockMovCR = 0x00008000, - /// Don't decode LOCK MOV CR0 as MOV CR8 (AMD) - [System.Obsolete("This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.", true)] - [System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)] - NoLockMovCR0 = 0x00008000, /// Don't decode TZCNT, decode BSF instead NoMPFX_0FBC = 0x00010000, /// Don't decode LZCNT, decode BSR instead diff --git a/src/csharp/Intel/Iced/Intel/OpCodeInfo.cs b/src/csharp/Intel/Iced/Intel/OpCodeInfo.cs index c33e6bd1d..a1faf394b 100644 --- a/src/csharp/Intel/Iced/Intel/OpCodeInfo.cs +++ b/src/csharp/Intel/Iced/Intel/OpCodeInfo.cs @@ -380,13 +380,6 @@ namespace Iced.Intel { /// public bool RequireOpMaskRegister => (encFlags3 & EncFlags3.RequireOpMaskRegister) != 0; - /// - /// (EVEX) if a non-zero opmask register must be used - /// - [System.Obsolete("Use " + nameof(RequireOpMaskRegister) + " instead", true)] - [System.ComponentModel.EditorBrowsable(System.ComponentModel.EditorBrowsableState.Never)] - public bool RequireNonZeroOpMaskRegister => RequireOpMaskRegister; - /// /// (EVEX) if the instruction supports zeroing masking (if one of the opmask registers K1-K7 is used and destination operand is not a memory operand) /// diff --git a/src/rust/iced-x86/src/decoder.rs b/src/rust/iced-x86/src/decoder.rs index b3fa0f3b5..5be819308 100644 --- a/src/rust/iced-x86/src/decoder.rs +++ b/src/rust/iced-x86/src/decoder.rs @@ -121,9 +121,6 @@ impl DecoderOptions { pub const NO_INVALID_CHECK: u32 = 0x0000_0001; /// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no `o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS`, `UD0` has no modr/m byte, decode `LOCK MOV CR`. The AMD decoder can still decode Intel instructions. pub const AMD: u32 = 0x0000_0002; - /// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode, no `o64 CALL/JMP FAR [mem], o64 LSS/LFS/LGS`, `UD0` has no modr/m byte, decode `LOCK MOV CR`. The AMD decoder can still decode Intel instructions. - #[deprecated(since = "1.8.0", note = "Use AMD instead")] - pub const AMD_BRANCHES: u32 = 0x0000_0002; /// Decode opcodes `0F0D` and `0F18-0F1F` as reserved-nop instructions (eg. [`Code::Reservednop_rm32_r32_0F1D`]) /// /// [`Code::Reservednop_rm32_r32_0F1D`]: enum.Code.html#variant.Reservednop_rm32_r32_0F1D @@ -155,9 +152,6 @@ impl DecoderOptions { /// Don't decode `LOCK MOV CR0` as `MOV CR8` (AMD) #[deprecated(since = "1.11.0", note = "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")] pub const NO_LOCK_MOV_CR: u32 = 0x0000_8000; - /// Don't decode `LOCK MOV CR0` as `MOV CR8` (AMD) - #[deprecated(since = "1.9.0", note = "This value isn't used by iced. LOCK MOV CR is only decoded if AMD is set.")] - pub const NO_LOCK_MOV_CR0: u32 = 0x0000_8000; /// Don't decode `TZCNT`, decode `BSF` instead pub const NO_MPFX_0FBC: u32 = 0x0001_0000; /// Don't decode `LZCNT`, decode `BSR` instead @@ -862,18 +856,6 @@ impl<'a> Decoder<'a> { mk_read_value! {self, u32, u32::from_le} } - /// This method can be called after calling [`decode()`] and [`decode_out()`] to check if the - /// decoded instruction is invalid because there's no more bytes left or because of bad input data. - /// - /// [`decode()`]: #method.decode - /// [`decode_out()`]: #method.decode_out - #[must_use] - #[inline] - #[deprecated(since = "1.8.0", note = "Use last_error() instead")] - pub fn invalid_no_more_bytes(&self) -> bool { - (self.state.flags & StateFlags::NO_MORE_BYTES) != 0 - } - /// Gets the last decoder error. Unless you need to know the reason it failed, /// it's better to check [`instruction.is_invalid()`]. /// diff --git a/src/rust/iced-x86/src/encoder/op_code.rs b/src/rust/iced-x86/src/encoder/op_code.rs index 3ba394c80..55add7cac 100644 --- a/src/rust/iced-x86/src/encoder/op_code.rs +++ b/src/rust/iced-x86/src/encoder/op_code.rs @@ -557,14 +557,6 @@ impl OpCodeInfo { (self.enc_flags3 & EncFlags3::REQUIRE_OP_MASK_REGISTER) != 0 } - /// (EVEX) `true` if a non-zero op mask register must be used - #[deprecated(since = "1.9.0", note = "Use require_op_mask_register() instead")] - #[must_use] - #[inline] - pub fn require_non_zero_op_mask_register(&self) -> bool { - self.require_op_mask_register() - } - /// (EVEX) `true` if the instruction supports zeroing masking (if one of the op mask registers `K1`-`K7` is used and destination operand is not a memory operand) #[must_use] #[inline]