mirror of https://github.com/nmlgc/ReC98.git
90 lines
1.8 KiB
NASM
90 lines
1.8 KiB
NASM
; First TH05 .PI assembly translation unit.
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.386
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.model use16 large SHARED
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locals
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include pc98.inc
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include libs/master.lib/master.inc
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extrn _PI_MASKS:word
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extrn _pi_mask_ptr:word
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extrn _pi_mask_y:word
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extrn _pi_put_masked_vram_offset:word
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.code SHARED
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@pi_mask_setup_egc_and_advance$qv procdesc near
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public @PI_PUT_MASKED_8_ROWLOOP$QIIIUI
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@pi_put_masked_8_rowloop$qiiiui proc near
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; Can't use ARG, because the function doesn't `PUSH BP`!
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@@stride_packed = word ptr [bp+2]
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@@w = word ptr [bp+4]
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@@top = word ptr [bp+6]
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@@left = word ptr [bp+8]
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@@mask_id equ ax
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@@h equ di
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; Each original row is first blitted to this fixed row in VRAM, before being
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; blitted to its actual destination with the EGC active.
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TEMP_ROW = RES_Y
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shl @@mask_id, 3 ; *= PI_MASK_H * word
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add @@mask_id, offset _PI_MASKS
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mov _pi_mask_ptr, @@mask_id
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mov bp, sp
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mov dx, @@left
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shr dx, 3
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mov ax, @@top
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shl ax, 6
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add dx, ax
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shr ax, 2
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add dx, ax
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mov _pi_put_masked_vram_offset, dx
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mov _pi_mask_y, 0
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@@put_row:
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push es
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call graph_pack_put_8_noclip pascal, 0, TEMP_ROW, es, si, @@w
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push ds
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push @@h
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push si
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mov di, _pi_put_masked_vram_offset
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add _pi_put_masked_vram_offset, ROW_SIZE
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cmp _pi_put_masked_vram_offset, PLANE_SIZE
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jb short @@next_row
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sub _pi_put_masked_vram_offset, PLANE_SIZE
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@@next_row:
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call @pi_mask_setup_egc_and_advance$qv
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mov ax, SEG_PLANE_B
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mov es, ax
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assume es:nothing
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mov ds, ax
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assume ds:nothing
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mov si, (ROW_SIZE * TEMP_ROW)
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mov cx, @@w
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shr cx, 4
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rep movsw
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call egc_off
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pop si
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pop @@h
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pop ds
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pop es
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add si, @@stride_packed
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; .PI pointer normalization, see pi_buffer_p_normalize()
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mov ax, si
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shr ax, 4
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mov dx, es
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add dx, ax
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mov es, dx
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and si, 0Fh
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dec @@h
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jnz short @@put_row
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retn 8
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@pi_put_masked_8_rowloop$qiiiui endp
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end
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