mirror of https://github.com/pyodide/pyodide.git
Add PyRTL package (#1628)
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parent
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@ -0,0 +1,15 @@
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package:
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name: pyrtl
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version: 0.10.0
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source:
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sha256: 7e01d2cc58e44d91055dd84e638e036c54350a4483977ab8066dd6e454440860
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url: https://files.pythonhosted.org/packages/d8/bb/8f2347627738827c15fc5ea2fd46cbf0784526ef288a8ce31f9c8fd5fb00/pyrtl-0.10.0.tar.gz
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patches:
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- patches/ctypes_and_renderer.patch
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requirements:
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run:
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- pyparsing
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- six
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test:
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imports:
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- pyrtl
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@ -0,0 +1,89 @@
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commit 30333d25771050779daac12c7779dd4b3836ab1f
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Author: Michael Christensen <chmdko@gmail.com>
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Date: Sat Jun 5 00:25:52 2021 -0700
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Move ctype import for Pyodide
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diff --git a/pyrtl/compilesim.py b/pyrtl/compilesim.py
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index 4ce0d45..5b82962 100644
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--- a/pyrtl/compilesim.py
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+++ b/pyrtl/compilesim.py
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@@ -1,6 +1,5 @@
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from __future__ import print_function, unicode_literals
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-import ctypes
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import subprocess
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import tempfile
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import shutil
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@@ -8,7 +7,6 @@ import collections
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from os import path
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import platform
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import sys
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-import _ctypes
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from .core import working_block
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from .wire import Input, Output, Const, WireVector, Register
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@@ -24,6 +22,8 @@ class DllMemInspector(collections.Mapping):
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""" Dictionary-like access to a hashmap in a CompiledSimulation. """
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def __init__(self, sim, mem):
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+ import ctypes
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+
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self._aw = mem.addrwidth
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self._limbs = sim._limbs(mem)
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self._vn = vn = sim.varname[mem]
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@@ -76,6 +76,14 @@ class CompiledSimulation(object):
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def __init__(
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self, tracer=True, register_value_map={}, memory_value_map={},
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default_value=0, block=None):
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+ try:
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+ import ctypes
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+ except ImportError:
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+ raise PyrtlError(
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+ 'need ctypes installed '
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+ '(try using normal Simulation or FastSimulation instead)'
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+ )
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+
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self._dll = self._dir = None
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self.block = working_block(block)
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self.block.sanity_check()
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@@ -239,6 +247,8 @@ class CompiledSimulation(object):
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:param inputs: A list of input mappings for each step;
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its length is the number of steps to be executed.
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"""
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+ import ctypes
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+
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steps = len(inputs)
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# create i/o arrays of the appropriate length
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ibuf_type = ctypes.c_uint64 * (steps * self._ibufsz)
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@@ -318,6 +328,8 @@ class CompiledSimulation(object):
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def _create_dll(self):
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""" Create a dynamically-linked library implementing the simulation logic. """
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+ import ctypes
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+
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self._dir = tempfile.mkdtemp()
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with open(path.join(self._dir, 'pyrtlsim.c'), 'w') as f:
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self._create_code(lambda s: f.write(s + '\n'))
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@@ -809,6 +821,8 @@ class CompiledSimulation(object):
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def __del__(self):
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"""Handle removal of the DLL when the simulator is deleted."""
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+ import _ctypes
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+
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if self._dll is not None:
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handle = self._dll._handle
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if platform.system() == 'Windows':
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diff --git a/pyrtl/simulation.py b/pyrtl/simulation.py
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index 3fbf751..14aaef2 100644
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--- a/pyrtl/simulation.py
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+++ b/pyrtl/simulation.py
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@@ -1127,7 +1127,7 @@ class SimulationTrace(object):
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file.flush()
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def render_trace(
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- self, trace_list=None, file=sys.stdout, render_cls=default_renderer(),
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+ self, trace_list=None, file=sys.stdout, render_cls=AsciiWaveRenderer,
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symbol_len=5, segment_size=5, segment_delim=' ', extra_line=True):
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""" Render the trace to a file using unicode and ASCII escape sequences.
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@ -0,0 +1,38 @@
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from pyodide_build.testing import run_in_pyodide
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@run_in_pyodide(packages=["pyrtl"])
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def test_pyrtl():
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import pyrtl
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# Calculate GCD of a and b
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a, b, begin = pyrtl.input_list("a/8 b/8 begin/1")
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gcd, done = pyrtl.output_list("gcd/8 done/1")
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x = pyrtl.Register(len(a))
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y = pyrtl.Register(len(b))
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with pyrtl.conditional_assignment:
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with begin:
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x.next |= a
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y.next |= b
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with x > y:
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x.next |= x - y
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with y > x:
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y.next |= y - x
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with pyrtl.otherwise:
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done |= True
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gcd <<= x
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sim = pyrtl.Simulation()
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sim.step(
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{
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"a": 56,
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"b": 42,
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"begin": 1,
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}
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)
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while sim.inspect("done") != 1:
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sim.step({"a": 0, "b": 0, "begin": 0})
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assert sim.inspect("gcd") == 14
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