Add PyRTL package (#1628)

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Michael Christensen 2021-06-06 00:59:35 -07:00 committed by GitHub
parent b9848db7df
commit 8932d6d938
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3 changed files with 142 additions and 0 deletions

15
packages/pyrtl/meta.yaml Normal file
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@ -0,0 +1,15 @@
package:
name: pyrtl
version: 0.10.0
source:
sha256: 7e01d2cc58e44d91055dd84e638e036c54350a4483977ab8066dd6e454440860
url: https://files.pythonhosted.org/packages/d8/bb/8f2347627738827c15fc5ea2fd46cbf0784526ef288a8ce31f9c8fd5fb00/pyrtl-0.10.0.tar.gz
patches:
- patches/ctypes_and_renderer.patch
requirements:
run:
- pyparsing
- six
test:
imports:
- pyrtl

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commit 30333d25771050779daac12c7779dd4b3836ab1f
Author: Michael Christensen <chmdko@gmail.com>
Date: Sat Jun 5 00:25:52 2021 -0700
Move ctype import for Pyodide
diff --git a/pyrtl/compilesim.py b/pyrtl/compilesim.py
index 4ce0d45..5b82962 100644
--- a/pyrtl/compilesim.py
+++ b/pyrtl/compilesim.py
@@ -1,6 +1,5 @@
from __future__ import print_function, unicode_literals
-import ctypes
import subprocess
import tempfile
import shutil
@@ -8,7 +7,6 @@ import collections
from os import path
import platform
import sys
-import _ctypes
from .core import working_block
from .wire import Input, Output, Const, WireVector, Register
@@ -24,6 +22,8 @@ class DllMemInspector(collections.Mapping):
""" Dictionary-like access to a hashmap in a CompiledSimulation. """
def __init__(self, sim, mem):
+ import ctypes
+
self._aw = mem.addrwidth
self._limbs = sim._limbs(mem)
self._vn = vn = sim.varname[mem]
@@ -76,6 +76,14 @@ class CompiledSimulation(object):
def __init__(
self, tracer=True, register_value_map={}, memory_value_map={},
default_value=0, block=None):
+ try:
+ import ctypes
+ except ImportError:
+ raise PyrtlError(
+ 'need ctypes installed '
+ '(try using normal Simulation or FastSimulation instead)'
+ )
+
self._dll = self._dir = None
self.block = working_block(block)
self.block.sanity_check()
@@ -239,6 +247,8 @@ class CompiledSimulation(object):
:param inputs: A list of input mappings for each step;
its length is the number of steps to be executed.
"""
+ import ctypes
+
steps = len(inputs)
# create i/o arrays of the appropriate length
ibuf_type = ctypes.c_uint64 * (steps * self._ibufsz)
@@ -318,6 +328,8 @@ class CompiledSimulation(object):
def _create_dll(self):
""" Create a dynamically-linked library implementing the simulation logic. """
+ import ctypes
+
self._dir = tempfile.mkdtemp()
with open(path.join(self._dir, 'pyrtlsim.c'), 'w') as f:
self._create_code(lambda s: f.write(s + '\n'))
@@ -809,6 +821,8 @@ class CompiledSimulation(object):
def __del__(self):
"""Handle removal of the DLL when the simulator is deleted."""
+ import _ctypes
+
if self._dll is not None:
handle = self._dll._handle
if platform.system() == 'Windows':
diff --git a/pyrtl/simulation.py b/pyrtl/simulation.py
index 3fbf751..14aaef2 100644
--- a/pyrtl/simulation.py
+++ b/pyrtl/simulation.py
@@ -1127,7 +1127,7 @@ class SimulationTrace(object):
file.flush()
def render_trace(
- self, trace_list=None, file=sys.stdout, render_cls=default_renderer(),
+ self, trace_list=None, file=sys.stdout, render_cls=AsciiWaveRenderer,
symbol_len=5, segment_size=5, segment_delim=' ', extra_line=True):
""" Render the trace to a file using unicode and ASCII escape sequences.

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from pyodide_build.testing import run_in_pyodide
@run_in_pyodide(packages=["pyrtl"])
def test_pyrtl():
import pyrtl
# Calculate GCD of a and b
a, b, begin = pyrtl.input_list("a/8 b/8 begin/1")
gcd, done = pyrtl.output_list("gcd/8 done/1")
x = pyrtl.Register(len(a))
y = pyrtl.Register(len(b))
with pyrtl.conditional_assignment:
with begin:
x.next |= a
y.next |= b
with x > y:
x.next |= x - y
with y > x:
y.next |= y - x
with pyrtl.otherwise:
done |= True
gcd <<= x
sim = pyrtl.Simulation()
sim.step(
{
"a": 56,
"b": 42,
"begin": 1,
}
)
while sim.inspect("done") != 1:
sim.step({"a": 0, "b": 0, "begin": 0})
assert sim.inspect("gcd") == 14