mirror of https://github.com/pret/pokeemerald.git
389 lines
17 KiB
C
389 lines
17 KiB
C
#ifndef GUARD_GBA_IO_REG_H
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#define GUARD_GBA_IO_REG_H
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#define REG_BASE 0x4000000 // I/O register base address
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// I/O register offsets
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#define REG_OFFSET_DISPCNT 0x0
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#define REG_OFFSET_DISPSTAT 0x4
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#define REG_OFFSET_VCOUNT 0x6
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#define REG_OFFSET_BG0CNT 0x8
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#define REG_OFFSET_BG1CNT 0xa
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#define REG_OFFSET_BG2CNT 0xc
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#define REG_OFFSET_BG3CNT 0xe
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#define REG_OFFSET_BG0HOFS 0x10
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#define REG_OFFSET_BG0VOFS 0x12
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#define REG_OFFSET_BG1HOFS 0x14
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#define REG_OFFSET_BG1VOFS 0x16
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#define REG_OFFSET_BG2HOFS 0x18
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#define REG_OFFSET_BG2VOFS 0x1a
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#define REG_OFFSET_BG3HOFS 0x1c
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#define REG_OFFSET_BG3VOFS 0x1e
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#define REG_OFFSET_BG2PA 0x20
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#define REG_OFFSET_BG2PB 0x22
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#define REG_OFFSET_BG2PC 0x24
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#define REG_OFFSET_BG2PD 0x26
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#define REG_OFFSET_BG2X_L 0x28
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#define REG_OFFSET_BG2X_H 0x2a
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#define REG_OFFSET_BG2Y_L 0x2c
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#define REG_OFFSET_BG2Y_H 0x2e
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#define REG_OFFSET_BG3PA 0x30
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#define REG_OFFSET_BG3PB 0x32
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#define REG_OFFSET_BG3PC 0x34
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#define REG_OFFSET_BG3PD 0x36
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#define REG_OFFSET_BG3X_L 0x38
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#define REG_OFFSET_BG3X_H 0x3a
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#define REG_OFFSET_BG3Y_L 0x3c
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#define REG_OFFSET_BG3Y_H 0x3e
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#define REG_OFFSET_WIN0H 0x40
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#define REG_OFFSET_WIN1H 0x42
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#define REG_OFFSET_WIN0V 0x44
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#define REG_OFFSET_WIN1V 0x46
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#define REG_OFFSET_WININ 0x48
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#define REG_OFFSET_WINOUT 0x4a
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#define REG_OFFSET_MOSAIC 0x4c
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#define REG_OFFSET_BLDCNT 0x50
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#define REG_OFFSET_BLDALPHA 0x52
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#define REG_OFFSET_BLDY 0x54
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#define REG_OFFSET_SOUND1CNT 0x60
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#define REG_OFFSET_SOUND1CNT_L 0x60
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#define REG_OFFSET_SOUND1CNT_H 0x62
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#define REG_OFFSET_SOUND1CNT_X 0x64
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#define REG_OFFSET_SOUND2CNT 0x68
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#define REG_OFFSET_SOUND2CNT_L 0x68
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#define REG_OFFSET_SOUND2CNT_H 0x6c
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#define REG_OFFSET_SOUND3CNT 0x70
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#define REG_OFFSET_SOUND3CNT_L 0x70
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#define REG_OFFSET_SOUND3CNT_H 0x72
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#define REG_OFFSET_SOUND3CNT_X 0x74
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#define REG_OFFSET_SOUND4CNT 0x78
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#define REG_OFFSET_SOUND4CNT_L 0x78
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#define REG_OFFSET_SOUND4CNT_H 0x7c
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#define REG_OFFSET_SOUNDCNT 0x80
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#define REG_OFFSET_SOUNDCNT_L 0x80
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#define REG_OFFSET_SOUNDCNT_H 0x82
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#define REG_OFFSET_SOUNDCNT_X 0x84
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#define REG_OFFSET_SOUNDBIAS 0x88
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#define REG_OFFSET_WAVE_RAM 0x90
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#define REG_OFFSET_WAVE_RAM0 0x90
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#define REG_OFFSET_WAVE_RAM0_L 0x90
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#define REG_OFFSET_WAVE_RAM0_H 0x92
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#define REG_OFFSET_WAVE_RAM1 0x94
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#define REG_OFFSET_WAVE_RAM1_L 0x94
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#define REG_OFFSET_WAVE_RAM1_H 0x96
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#define REG_OFFSET_WAVE_RAM2 0x98
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#define REG_OFFSET_WAVE_RAM2_L 0x98
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#define REG_OFFSET_WAVE_RAM2_H 0x9a
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#define REG_OFFSET_WAVE_RAM3 0x9c
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#define REG_OFFSET_WAVE_RAM3_L 0x9c
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#define REG_OFFSET_WAVE_RAM3_H 0x9e
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#define REG_OFFSET_FIFO 0xa0
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#define REG_OFFSET_FIFO_A 0xa0
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#define REG_OFFSET_FIFO_A_L 0xa0
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#define REG_OFFSET_FIFO_A_H 0xa2
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#define REG_OFFSET_FIFO_B 0xa4
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#define REG_OFFSET_FIFO_B_L 0xa4
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#define REG_OFFSET_FIFO_B_H 0xa6
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#define REG_OFFSET_DMA0 0xb0
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#define REG_OFFSET_DMA0SAD 0xb0
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#define REG_OFFSET_DMA0SAD_L 0xb0
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#define REG_OFFSET_DMA0SAD_H 0xb2
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#define REG_OFFSET_DMA0DAD 0xb4
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#define REG_OFFSET_DMA0DAD_L 0xb4
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#define REG_OFFSET_DMA0DAD_H 0xb6
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#define REG_OFFSET_DMA0CNT 0xb8
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#define REG_OFFSET_DMA0CNT_L 0xb8
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#define REG_OFFSET_DMA0CNT_H 0xba
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#define REG_OFFSET_DMA1 0xbc
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#define REG_OFFSET_DMA1SAD 0xbc
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#define REG_OFFSET_DMA1SAD_L 0xbc
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#define REG_OFFSET_DMA1SAD_H 0xbe
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#define REG_OFFSET_DMA1DAD 0xc0
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#define REG_OFFSET_DMA1DAD_L 0xc0
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#define REG_OFFSET_DMA1DAD_H 0xc2
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#define REG_OFFSET_DMA1CNT 0xc4
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#define REG_OFFSET_DMA1CNT_L 0xc4
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#define REG_OFFSET_DMA1CNT_H 0xc6
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#define REG_OFFSET_DMA2 0xc8
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#define REG_OFFSET_DMA2SAD 0xc8
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#define REG_OFFSET_DMA2SAD_L 0xc8
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#define REG_OFFSET_DMA2SAD_H 0xca
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#define REG_OFFSET_DMA2DAD 0xcc
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#define REG_OFFSET_DMA2DAD_L 0xcc
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#define REG_OFFSET_DMA2DAD_H 0xce
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#define REG_OFFSET_DMA2CNT 0xd0
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#define REG_OFFSET_DMA2CNT_L 0xd0
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#define REG_OFFSET_DMA2CNT_H 0xd2
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#define REG_OFFSET_DMA3 0xd4
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#define REG_OFFSET_DMA3SAD 0xd4
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#define REG_OFFSET_DMA3SAD_L 0xd4
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#define REG_OFFSET_DMA3SAD_H 0xd6
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#define REG_OFFSET_DMA3DAD 0xd8
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#define REG_OFFSET_DMA3DAD_L 0xd8
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#define REG_OFFSET_DMA3DAD_H 0xda
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#define REG_OFFSET_DMA3CNT 0xdc
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#define REG_OFFSET_DMA3CNT_L 0xdc
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#define REG_OFFSET_DMA3CNT_H 0xde
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#define REG_OFFSET_TM0CNT 0x100
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#define REG_OFFSET_TM0CNT_L 0x100
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#define REG_OFFSET_TM0CNT_H 0x102
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#define REG_OFFSET_TM1CNT 0x104
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#define REG_OFFSET_TM1CNT_L 0x104
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#define REG_OFFSET_TM1CNT_H 0x106
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#define REG_OFFSET_TM2CNT 0x108
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#define REG_OFFSET_TM2CNT_L 0x108
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#define REG_OFFSET_TM2CNT_H 0x10a
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#define REG_OFFSET_TM3CNT 0x10c
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#define REG_OFFSET_TM3CNT_L 0x10c
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#define REG_OFFSET_TM3CNT_H 0x10e
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#define REG_OFFSET_SIOCNT 0x128
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#define REG_OFFSET_SIODATA8 0x12a
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#define REG_OFFSET_SIODATA32 0x120
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#define REG_OFFSET_SIOMLT_SEND 0x12a
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#define REG_OFFSET_SIOMLT_RECV 0x120
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#define REG_OFFSET_SIOMULTI0 0x120
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#define REG_OFFSET_SIOMULTI1 0x122
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#define REG_OFFSET_SIOMULTI2 0x124
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#define REG_OFFSET_SIOMULTI3 0x126
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#define REG_OFFSET_KEYINPUT 0x130
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#define REG_OFFSET_KEYCNT 0x132
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#define REG_OFFSET_RCNT 0x134
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#define REG_OFFSET_JOYCNT 0x140
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#define REG_OFFSET_JOYSTAT 0x158
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#define REG_OFFSET_JOY_RECV 0x150
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#define REG_OFFSET_JOY_RECV_L 0x150
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#define REG_OFFSET_JOY_RECV_H 0x152
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#define REG_OFFSET_JOY_TRANS 0x154
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#define REG_OFFSET_JOY_TRANS_L 0x154
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#define REG_OFFSET_JOY_TRANS_H 0x156
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#define REG_OFFSET_IME 0x208
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#define REG_OFFSET_IE 0x200
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#define REG_OFFSET_IF 0x202
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#define REG_OFFSET_WAITCNT 0x204
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// I/O register addresses
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#define REG_ADDR_DISPCNT (REG_BASE + REG_OFFSET_DISPCNT)
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#define REG_ADDR_DISPSTAT (REG_BASE + REG_OFFSET_DISPSTAT)
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#define REG_ADDR_VCOUNT (REG_BASE + REG_OFFSET_VCOUNT)
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#define REG_ADDR_BG0CNT (REG_BASE + REG_OFFSET_BG0CNT)
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#define REG_ADDR_BG1CNT (REG_BASE + REG_OFFSET_BG1CNT)
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#define REG_ADDR_BG2CNT (REG_BASE + REG_OFFSET_BG2CNT)
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#define REG_ADDR_BG3CNT (REG_BASE + REG_OFFSET_BG3CNT)
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#define REG_ADDR_BG0HOFS (REG_BASE + REG_OFFSET_BG0HOFS)
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#define REG_ADDR_BG0VOFS (REG_BASE + REG_OFFSET_BG0VOFS)
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#define REG_ADDR_BG1HOFS (REG_BASE + REG_OFFSET_BG1HOFS)
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#define REG_ADDR_BG1VOFS (REG_BASE + REG_OFFSET_BG1VOFS)
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#define REG_ADDR_BG2HOFS (REG_BASE + REG_OFFSET_BG2HOFS)
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#define REG_ADDR_BG2VOFS (REG_BASE + REG_OFFSET_BG2VOFS)
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#define REG_ADDR_BG3HOFS (REG_BASE + REG_OFFSET_BG3HOFS)
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#define REG_ADDR_BG3VOFS (REG_BASE + REG_OFFSET_BG3VOFS)
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#define REG_ADDR_BG2PA (REG_BASE + REG_OFFSET_BG2PA)
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#define REG_ADDR_BG2PB (REG_BASE + REG_OFFSET_BG2PB)
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#define REG_ADDR_BG2PC (REG_BASE + REG_OFFSET_BG2PC)
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#define REG_ADDR_BG2PD (REG_BASE + REG_OFFSET_BG2PD)
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#define REG_ADDR_BG2X_L (REG_BASE + REG_OFFSET_BG2X_L)
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#define REG_ADDR_BG2X_H (REG_BASE + REG_OFFSET_BG2X_H)
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#define REG_ADDR_BG2Y_L (REG_BASE + REG_OFFSET_BG2Y_L)
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#define REG_ADDR_BG2Y_H (REG_BASE + REG_OFFSET_BG2Y_H)
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#define REG_ADDR_BG3PA (REG_BASE + REG_OFFSET_BG3PA)
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#define REG_ADDR_BG3PB (REG_BASE + REG_OFFSET_BG3PB)
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#define REG_ADDR_BG3PC (REG_BASE + REG_OFFSET_BG3PC)
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#define REG_ADDR_BG3PD (REG_BASE + REG_OFFSET_BG3PD)
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#define REG_ADDR_BG3X_L (REG_BASE + REG_OFFSET_BG3X_L)
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#define REG_ADDR_BG3X_H (REG_BASE + REG_OFFSET_BG3X_H)
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#define REG_ADDR_BG3Y_L (REG_BASE + REG_OFFSET_BG3Y_L)
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#define REG_ADDR_BG3Y_H (REG_BASE + REG_OFFSET_BG3Y_H)
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#define REG_ADDR_WIN0H (REG_BASE + REG_OFFSET_WIN0H)
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#define REG_ADDR_WIN1H (REG_BASE + REG_OFFSET_WIN1H)
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#define REG_ADDR_WIN0V (REG_BASE + REG_OFFSET_WIN0V)
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#define REG_ADDR_WIN1V (REG_BASE + REG_OFFSET_WIN1V)
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#define REG_ADDR_WININ (REG_BASE + REG_OFFSET_WININ)
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#define REG_ADDR_WINOUT (REG_BASE + REG_OFFSET_WINOUT)
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#define REG_ADDR_MOSAIC (REG_BASE + REG_OFFSET_MOSAIC)
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#define REG_ADDR_BLDCNT (REG_BASE + REG_OFFSET_BLDCNT)
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#define REG_ADDR_BLDALPHA (REG_BASE + REG_OFFSET_BLDALPHA)
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#define REG_ADDR_BLDY (REG_BASE + REG_OFFSET_BLDY)
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#define REG_ADDR_SOUND1CNT (REG_BASE + REG_OFFSET_SOUND1CNT)
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#define REG_ADDR_SOUND1CNT_L (REG_BASE + REG_OFFSET_SOUND1CNT_L)
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#define REG_ADDR_SOUND1CNT_H (REG_BASE + REG_OFFSET_SOUND1CNT_H)
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#define REG_ADDR_SOUND1CNT_X (REG_BASE + REG_OFFSET_SOUND1CNT_X)
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#define REG_ADDR_SOUND2CNT (REG_BASE + REG_OFFSET_SOUND2CNT)
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#define REG_ADDR_SOUND2CNT_L (REG_BASE + REG_OFFSET_SOUND2CNT_L)
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#define REG_ADDR_SOUND2CNT_H (REG_BASE + REG_OFFSET_SOUND2CNT_H)
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#define REG_ADDR_SOUND3CNT (REG_BASE + REG_OFFSET_SOUND3CNT)
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#define REG_ADDR_SOUND3CNT_L (REG_BASE + REG_OFFSET_SOUND3CNT_L)
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#define REG_ADDR_SOUND3CNT_H (REG_BASE + REG_OFFSET_SOUND3CNT_H)
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#define REG_ADDR_SOUND3CNT_X (REG_BASE + REG_OFFSET_SOUND3CNT_X)
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#define REG_ADDR_SOUND4CNT (REG_BASE + REG_OFFSET_SOUND4CNT)
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#define REG_ADDR_SOUND4CNT_L (REG_BASE + REG_OFFSET_SOUND4CNT_L)
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#define REG_ADDR_SOUND4CNT_H (REG_BASE + REG_OFFSET_SOUND4CNT_H)
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#define REG_ADDR_SOUNDCNT (REG_BASE + REG_OFFSET_SOUNDCNT)
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#define REG_ADDR_SOUNDCNT_L (REG_BASE + REG_OFFSET_SOUNDCNT_L)
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#define REG_ADDR_SOUNDCNT_H (REG_BASE + REG_OFFSET_SOUNDCNT_H)
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#define REG_ADDR_SOUNDCNT_X (REG_BASE + REG_OFFSET_SOUNDCNT_X)
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#define REG_ADDR_SOUNDBIAS (REG_BASE + REG_OFFSET_SOUNDBIAS)
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#define REG_ADDR_WAVE_RAM (REG_BASE + REG_OFFSET_WAVE_RAM)
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#define REG_ADDR_WAVE_RAM0 (REG_BASE + REG_OFFSET_WAVE_RAM0)
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#define REG_ADDR_WAVE_RAM0_L (REG_BASE + REG_OFFSET_WAVE_RAM0_L)
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#define REG_ADDR_WAVE_RAM0_H (REG_BASE + REG_OFFSET_WAVE_RAM0_H)
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#define REG_ADDR_WAVE_RAM1 (REG_BASE + REG_OFFSET_WAVE_RAM1)
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#define REG_ADDR_WAVE_RAM1_L (REG_BASE + REG_OFFSET_WAVE_RAM1_L)
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#define REG_ADDR_WAVE_RAM1_H (REG_BASE + REG_OFFSET_WAVE_RAM1_H)
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#define REG_ADDR_WAVE_RAM2 (REG_BASE + REG_OFFSET_WAVE_RAM2)
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#define REG_ADDR_WAVE_RAM2_L (REG_BASE + REG_OFFSET_WAVE_RAM2_L)
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#define REG_ADDR_WAVE_RAM2_H (REG_BASE + REG_OFFSET_WAVE_RAM2_H)
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#define REG_ADDR_WAVE_RAM3 (REG_BASE + REG_OFFSET_WAVE_RAM3)
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#define REG_ADDR_WAVE_RAM3_L (REG_BASE + REG_OFFSET_WAVE_RAM3_L)
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#define REG_ADDR_WAVE_RAM3_H (REG_BASE + REG_OFFSET_WAVE_RAM3_H)
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#define REG_ADDR_FIFO (REG_BASE + REG_OFFSET_FIFO)
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#define REG_ADDR_FIFO_A (REG_BASE + REG_OFFSET_FIFO_A)
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#define REG_ADDR_FIFO_A_L (REG_BASE + REG_OFFSET_FIFO_A_L)
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#define REG_ADDR_FIFO_A_H (REG_BASE + REG_OFFSET_FIFO_A_H)
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#define REG_ADDR_FIFO_B (REG_BASE + REG_OFFSET_FIFO_B)
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#define REG_ADDR_FIFO_B_L (REG_BASE + REG_OFFSET_FIFO_B_L)
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#define REG_ADDR_FIFO_B_H (REG_BASE + REG_OFFSET_FIFO_B_H)
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#define REG_ADDR_DMA0 (REG_BASE + REG_OFFSET_DMA0)
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#define REG_ADDR_DMA0SAD (REG_BASE + REG_OFFSET_DMA0SAD)
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#define REG_ADDR_DMA0SAD_L (REG_BASE + REG_OFFSET_DMA0SAD_L)
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#define REG_ADDR_DMA0SAD_H (REG_BASE + REG_OFFSET_DMA0SAD_H)
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#define REG_ADDR_DMA0DAD (REG_BASE + REG_OFFSET_DMA0DAD)
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#define REG_ADDR_DMA0DAD_L (REG_BASE + REG_OFFSET_DMA0DAD_L)
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#define REG_ADDR_DMA0DAD_H (REG_BASE + REG_OFFSET_DMA0DAD_H)
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#define REG_ADDR_DMA0CNT (REG_BASE + REG_OFFSET_DMA0CNT)
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#define REG_ADDR_DMA0CNT_L (REG_BASE + REG_OFFSET_DMA0CNT_L)
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#define REG_ADDR_DMA0CNT_H (REG_BASE + REG_OFFSET_DMA0CNT_H)
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#define REG_ADDR_DMA1 (REG_BASE + REG_OFFSET_DMA1)
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#define REG_ADDR_DMA1SAD (REG_BASE + REG_OFFSET_DMA1SAD)
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#define REG_ADDR_DMA1SAD_L (REG_BASE + REG_OFFSET_DMA1SAD_L)
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#define REG_ADDR_DMA1SAD_H (REG_BASE + REG_OFFSET_DMA1SAD_H)
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#define REG_ADDR_DMA1DAD (REG_BASE + REG_OFFSET_DMA1DAD)
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#define REG_ADDR_DMA1DAD_L (REG_BASE + REG_OFFSET_DMA1DAD_L)
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#define REG_ADDR_DMA1DAD_H (REG_BASE + REG_OFFSET_DMA1DAD_H)
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#define REG_ADDR_DMA1CNT (REG_BASE + REG_OFFSET_DMA1CNT)
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#define REG_ADDR_DMA1CNT_L (REG_BASE + REG_OFFSET_DMA1CNT_L)
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#define REG_ADDR_DMA1CNT_H (REG_BASE + REG_OFFSET_DMA1CNT_H)
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#define REG_ADDR_DMA2 (REG_BASE + REG_OFFSET_DMA2)
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#define REG_ADDR_DMA2SAD (REG_BASE + REG_OFFSET_DMA2SAD)
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#define REG_ADDR_DMA2SAD_L (REG_BASE + REG_OFFSET_DMA2SAD_L)
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#define REG_ADDR_DMA2SAD_H (REG_BASE + REG_OFFSET_DMA2SAD_H)
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#define REG_ADDR_DMA2DAD (REG_BASE + REG_OFFSET_DMA2DAD)
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#define REG_ADDR_DMA2DAD_L (REG_BASE + REG_OFFSET_DMA2DAD_L)
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#define REG_ADDR_DMA2DAD_H (REG_BASE + REG_OFFSET_DMA2DAD_H)
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#define REG_ADDR_DMA2CNT (REG_BASE + REG_OFFSET_DMA2CNT)
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#define REG_ADDR_DMA2CNT_L (REG_BASE + REG_OFFSET_DMA2CNT_L)
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#define REG_ADDR_DMA2CNT_H (REG_BASE + REG_OFFSET_DMA2CNT_H)
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#define REG_ADDR_DMA3 (REG_BASE + REG_OFFSET_DMA3)
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#define REG_ADDR_DMA3SAD (REG_BASE + REG_OFFSET_DMA3SAD)
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#define REG_ADDR_DMA3SAD_L (REG_BASE + REG_OFFSET_DMA3SAD_L)
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#define REG_ADDR_DMA3SAD_H (REG_BASE + REG_OFFSET_DMA3SAD_H)
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#define REG_ADDR_DMA3DAD (REG_BASE + REG_OFFSET_DMA3DAD)
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#define REG_ADDR_DMA3DAD_L (REG_BASE + REG_OFFSET_DMA3DAD_L)
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#define REG_ADDR_DMA3DAD_H (REG_BASE + REG_OFFSET_DMA3DAD_H)
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#define REG_ADDR_DMA3CNT (REG_BASE + REG_OFFSET_DMA3CNT)
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#define REG_ADDR_DMA3CNT_L (REG_BASE + REG_OFFSET_DMA3CNT_L)
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#define REG_ADDR_DMA3CNT_H (REG_BASE + REG_OFFSET_DMA3CNT_H)
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#define REG_ADDR_TM0CNT (REG_BASE + REG_OFFSET_TM0CNT)
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#define REG_ADDR_TM0CNT_L (REG_BASE + REG_OFFSET_TM0CNT_L)
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#define REG_ADDR_TM0CNT_H (REG_BASE + REG_OFFSET_TM0CNT_H)
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#define REG_ADDR_TM1CNT (REG_BASE + REG_OFFSET_TM1CNT)
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#define REG_ADDR_TM1CNT_L (REG_BASE + REG_OFFSET_TM1CNT_L)
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#define REG_ADDR_TM1CNT_H (REG_BASE + REG_OFFSET_TM1CNT_H)
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#define REG_ADDR_TM2CNT (REG_BASE + REG_OFFSET_TM2CNT)
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#define REG_ADDR_TM2CNT_L (REG_BASE + REG_OFFSET_TM2CNT_L)
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#define REG_ADDR_TM2CNT_H (REG_BASE + REG_OFFSET_TM2CNT_H)
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#define REG_ADDR_TM3CNT (REG_BASE + REG_OFFSET_TM3CNT)
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#define REG_ADDR_TM3CNT_L (REG_BASE + REG_OFFSET_TM3CNT_L)
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#define REG_ADDR_TM3CNT_H (REG_BASE + REG_OFFSET_TM3CNT_H)
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#define REG_ADDR_SIOCNT (REG_BASE + REG_OFFSET_SIOCNT)
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#define REG_ADDR_SIODATA8 (REG_BASE + REG_OFFSET_SIODATA8)
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#define REG_ADDR_SIODATA32 (REG_BASE + REG_OFFSET_SIODATA32)
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#define REG_ADDR_SIOMLT_SEND (REG_BASE + REG_OFFSET_SIOMLT_SEND)
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#define REG_ADDR_SIOMLT_RECV (REG_BASE + REG_OFFSET_SIOMLT_RECV)
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#define REG_ADDR_SIOMULTI0 (REG_BASE + REG_OFFSET_SIOMULTI0)
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#define REG_ADDR_SIOMULTI1 (REG_BASE + REG_OFFSET_SIOMULTI1)
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#define REG_ADDR_SIOMULTI2 (REG_BASE + REG_OFFSET_SIOMULTI2)
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#define REG_ADDR_SIOMULTI3 (REG_BASE + REG_OFFSET_SIOMULTI3)
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#define REG_ADDR_KEYINPUT (REG_BASE + REG_OFFSET_KEYINPUT)
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#define REG_ADDR_KEYCNT (REG_BASE + REG_OFFSET_KEYCNT)
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#define REG_ADDR_RCNT (REG_BASE + REG_OFFSET_RCNT)
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#define REG_ADDR_JOYCNT (REG_BASE + REG_OFFSET_JOYCNT)
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#define REG_ADDR_JOYSTAT (REG_BASE + REG_OFFSET_JOYSTAT)
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#define REG_ADDR_JOY_RECV (REG_BASE + REG_OFFSET_JOY_RECV)
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#define REG_ADDR_JOY_RECV_L (REG_BASE + REG_OFFSET_JOY_RECV_L)
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#define REG_ADDR_JOY_RECV_H (REG_BASE + REG_OFFSET_JOY_RECV_H)
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#define REG_ADDR_JOY_TRANS (REG_BASE + REG_OFFSET_JOY_TRANS)
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#define REG_ADDR_JOY_TRANS_L (REG_BASE + REG_OFFSET_JOY_TRANS_L)
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#define REG_ADDR_JOY_TRANS_H (REG_BASE + REG_OFFSET_JOY_TRANS_H)
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#define REG_ADDR_IME (REG_BASE + REG_OFFSET_IME)
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#define REG_ADDR_IE (REG_BASE + REG_OFFSET_IE)
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#define REG_ADDR_IF (REG_BASE + REG_OFFSET_IF)
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#define REG_ADDR_WAITCNT (REG_BASE + REG_OFFSET_WAITCNT)
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// I/O registers
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#define REG_DISPCNT (*(vu32 *)REG_ADDR_DISPCNT)
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#define REG_DISPSTAT (*(vu16 *)REG_ADDR_DISPSTAT)
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#define REG_VCOUNT (*(vu16 *)REG_ADDR_VCOUNT)
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#define REG_IME (*(vu16 *)REG_ADDR_IME)
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#define REG_IE (*(vu16 *)REG_ADDR_IE)
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#define REG_IF (*(vu16 *)REG_ADDR_IF)
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// I/O register fields
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// DISPCNT
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#define DISPCNT_MODE_0 0x0000
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#define DISPCNT_MODE_1 0x0001
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#define DISPCNT_MODE_2 0x0002
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#define DISPCNT_MODE_3 0x0003
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#define DISPCNT_MODE_4 0x0004
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#define DISPCNT_MODE_5 0x0005
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#define DISPCNT_OBJ_1D_MAP 0x0040
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#define DISPCNT_FORCED_BLANK 0x0080
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// DISPSTAT
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#define DISPSTAT_VBLANK 0x0001 // in V-Blank
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#define DISPSTAT_HBLANK 0x0002 // in H-Blank
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#define DISPSTAT_VCOUNT 0x0004 // V-Count match
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#define DISPSTAT_VBLANK_INTR 0x0008 // V-Blank interrupt enabled
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#define DISPSTAT_HBLANK_INTR 0x0010 // H-Blank interrupt enabled
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#define DISPSTAT_VCOUNT_INTR 0x0020 // V-Count interrupt enabled
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// interrupt flags
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#define INTR_FLAG_VBLANK (1 << 0)
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#define INTR_FLAG_HBLANK (1 << 1)
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#define INTR_FLAG_VCOUNT (1 << 2)
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#define INTR_FLAG_TIMER0 (1 << 3)
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#define INTR_FLAG_TIMER1 (1 << 4)
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#define INTR_FLAG_TIMER2 (1 << 5)
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#define INTR_FLAG_TIMER3 (1 << 6)
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#define INTR_FLAG_SERIAL (1 << 7)
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#define INTR_FLAG_DMA0 (1 << 8)
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#define INTR_FLAG_DMA1 (1 << 9)
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#define INTR_FLAG_DMA2 (1 << 10)
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#define INTR_FLAG_DMA3 (1 << 11)
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#define INTR_FLAG_KEYPAD (1 << 12)
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#define INTR_FLAG_GAMEPAK (1 << 13)
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#endif // GUARD_GBA_IO_REG_H
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