2013-02-20 05:05:07 +00:00
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; Graciously aped from http://nocash.emubase.de/pandocs.htm .
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2013-05-03 02:13:30 +00:00
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; MBC3
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MBC3SRamEnable EQU $0000
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MBC3RomBank EQU $2000
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MBC3SRamBank EQU $4000
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MBC3LatchClock EQU $6000
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MBC3RTC EQU $a000
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SRAM_DISABLE EQU $00
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SRAM_ENABLE EQU $0a
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2013-06-11 01:56:34 +00:00
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NUM_SRAM_BANKS EQU 4
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2013-05-03 02:13:30 +00:00
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RTC_S EQU $08 ; Seconds 0-59 (0-3Bh)
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RTC_M EQU $09 ; Minutes 0-59 (0-3Bh)
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RTC_H EQU $0a ; Hours 0-23 (0-17h)
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RTC_DL EQU $0b ; Lower 8 bits of Day Counter (0-FFh)
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RTC_DH EQU $0c ; Upper 1 bit of Day Counter, Carry Bit, Halt Flag
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; Bit 0 Most significant bit of Day Counter (Bit 8)
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; Bit 6 Halt (0=Active, 1=Stop Timer)
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; Bit 7 Day Counter Carry Bit (1=Counter Overflow)
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2013-08-28 03:37:24 +00:00
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; interrupt flags
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VBLANK EQU 0
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LCD_STAT EQU 1
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TIMER EQU 2
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SERIAL EQU 3
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JOYPAD EQU 4
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2013-05-03 02:13:30 +00:00
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2013-12-01 21:40:56 +00:00
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; OAM attribute flags
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OAM_PALETTE EQU %111
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OAM_TILE_BANK EQU 3
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OAM_OBP_NUM EQU 4 ; Non CGB Mode Only
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OAM_X_FLIP EQU 5
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OAM_Y_FLIP EQU 6
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OAM_PRIORITY EQU 7 ; 0: OBJ above BG, 1: OBJ behind BG (colors 1-3)
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2017-12-09 05:50:59 +00:00
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X_FLIP EQU 1 << OAM_X_FLIP
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Y_FLIP EQU 1 << OAM_Y_FLIP
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BEHIND_BG EQU 1 << OAM_PRIORITY
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2013-12-01 21:40:56 +00:00
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2013-05-03 02:13:30 +00:00
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; Hardware registers
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2013-02-20 05:05:07 +00:00
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rJOYP EQU $ff00 ; Joypad (R/W)
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rSB EQU $ff01 ; Serial transfer data (R/W)
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rSC EQU $ff02 ; Serial Transfer Control (R/W)
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2013-08-28 03:37:24 +00:00
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rSC_ON EQU 7
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rSC_CGB EQU 1
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rSC_CLOCK EQU 0
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2013-02-20 05:05:07 +00:00
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rDIV EQU $ff04 ; Divider Register (R/W)
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rTIMA EQU $ff05 ; Timer counter (R/W)
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rTMA EQU $ff06 ; Timer Modulo (R/W)
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rTAC EQU $ff07 ; Timer Control (R/W)
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2013-08-28 03:37:24 +00:00
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rTAC_ON EQU 2
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rTAC_4096_HZ EQU 0
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rTAC_262144_HZ EQU 1
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2015-07-19 03:45:39 +00:00
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rTAC_65536_HZ EQU 2
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2013-08-28 03:37:24 +00:00
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rTAC_16384_HZ EQU 3
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2013-02-20 05:05:07 +00:00
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rIF EQU $ff0f ; Interrupt Flag (R/W)
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rNR10 EQU $ff10 ; Channel 1 Sweep register (R/W)
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rNR11 EQU $ff11 ; Channel 1 Sound length/Wave pattern duty (R/W)
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rNR12 EQU $ff12 ; Channel 1 Volume Envelope (R/W)
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rNR13 EQU $ff13 ; Channel 1 Frequency lo (Write Only)
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rNR14 EQU $ff14 ; Channel 1 Frequency hi (R/W)
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2015-11-10 04:01:45 +00:00
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rNR20 EQU $ff15 ; Channel 2 Sweep register (R/W)
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2013-02-20 05:05:07 +00:00
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rNR21 EQU $ff16 ; Channel 2 Sound Length/Wave Pattern Duty (R/W)
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rNR22 EQU $ff17 ; Channel 2 Volume Envelope (R/W)
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rNR23 EQU $ff18 ; Channel 2 Frequency lo data (W)
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rNR24 EQU $ff19 ; Channel 2 Frequency hi data (R/W)
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rNR30 EQU $ff1a ; Channel 3 Sound on/off (R/W)
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rNR31 EQU $ff1b ; Channel 3 Sound Length
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rNR32 EQU $ff1c ; Channel 3 Select output level (R/W)
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rNR33 EQU $ff1d ; Channel 3 Frequency's lower data (W)
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rNR34 EQU $ff1e ; Channel 3 Frequency's higher data (R/W)
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2015-11-10 04:01:45 +00:00
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rNR40 EQU $ff1f ; Channel 4 Sweep register (R/W)
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2013-02-20 05:05:07 +00:00
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rNR41 EQU $ff20 ; Channel 4 Sound Length (R/W)
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rNR42 EQU $ff21 ; Channel 4 Volume Envelope (R/W)
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rNR43 EQU $ff22 ; Channel 4 Polynomial Counter (R/W)
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rNR44 EQU $ff23 ; Channel 4 Counter/consecutive; Inital (R/W)
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rNR50 EQU $ff24 ; Channel control / ON-OFF / Volume (R/W)
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rNR51 EQU $ff25 ; Selection of Sound output terminal (R/W)
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rNR52 EQU $ff26 ; Sound on/off
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2015-11-10 04:01:45 +00:00
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rWave_0 EQU $ff30
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rWave_1 EQU $ff31
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rWave_2 EQU $ff32
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rWave_3 EQU $ff33
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rWave_4 EQU $ff34
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rWave_5 EQU $ff35
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rWave_6 EQU $ff36
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rWave_7 EQU $ff37
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rWave_8 EQU $ff38
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rWave_9 EQU $ff39
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rWave_a EQU $ff3a
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rWave_b EQU $ff3b
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rWave_c EQU $ff3c
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rWave_d EQU $ff3d
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rWave_e EQU $ff3e
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rWave_f EQU $ff3f
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2013-02-20 05:05:07 +00:00
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rLCDC EQU $ff40 ; LCD Control (R/W)
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rSTAT EQU $ff41 ; LCDC Status (R/W)
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rSCY EQU $ff42 ; Scroll Y (R/W)
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rSCX EQU $ff43 ; Scroll X (R/W)
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rLY EQU $ff44 ; LCDC Y-Coordinate (R)
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rLYC EQU $ff45 ; LY Compare (R/W)
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rDMA EQU $ff46 ; DMA Transfer and Start Address (W)
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rBGP EQU $ff47 ; BG Palette Data (R/W) - Non CGB Mode Only
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rOBP0 EQU $ff48 ; Object Palette 0 Data (R/W) - Non CGB Mode Only
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rOBP1 EQU $ff49 ; Object Palette 1 Data (R/W) - Non CGB Mode Only
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rWY EQU $ff4a ; Window Y Position (R/W)
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rWX EQU $ff4b ; Window X Position minus 7 (R/W)
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2015-12-07 03:36:09 +00:00
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rLCDMODE EQU $ff4c
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2013-02-20 05:05:07 +00:00
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rKEY1 EQU $ff4d ; CGB Mode Only - Prepare Speed Switch
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rVBK EQU $ff4f ; CGB Mode Only - VRAM Bank
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2015-12-07 03:36:09 +00:00
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rBLCK EQU $ff50
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2013-02-20 05:05:07 +00:00
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rHDMA1 EQU $ff51 ; CGB Mode Only - New DMA Source, High
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rHDMA2 EQU $ff52 ; CGB Mode Only - New DMA Source, Low
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rHDMA3 EQU $ff53 ; CGB Mode Only - New DMA Destination, High
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rHDMA4 EQU $ff54 ; CGB Mode Only - New DMA Destination, Low
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rHDMA5 EQU $ff55 ; CGB Mode Only - New DMA Length/Mode/Start
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rRP EQU $ff56 ; CGB Mode Only - Infrared Communications Port
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rBGPI EQU $ff68 ; CGB Mode Only - Background Palette Index
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rBGPD EQU $ff69 ; CGB Mode Only - Background Palette Data
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rOBPI EQU $ff6a ; CGB Mode Only - Sprite Palette Index
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rOBPD EQU $ff6b ; CGB Mode Only - Sprite Palette Data
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rUNKNOWN1 EQU $ff6c ; (FEh) Bit 0 (Read/Write) - CGB Mode Only
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rSVBK EQU $ff70 ; CGB Mode Only - WRAM Bank
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rUNKNOWN2 EQU $ff72 ; (00h) - Bit 0-7 (Read/Write)
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rUNKNOWN3 EQU $ff73 ; (00h) - Bit 0-7 (Read/Write)
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rUNKNOWN4 EQU $ff74 ; (00h) - Bit 0-7 (Read/Write) - CGB Mode Only
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rUNKNOWN5 EQU $ff75 ; (8Fh) - Bit 4-6 (Read/Write)
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rUNKNOWN6 EQU $ff76 ; (00h) - Always 00h (Read Only)
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rUNKNOWN7 EQU $ff77 ; (00h) - Always 00h (Read Only)
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rIE EQU $ffff ; Interrupt Enable (R/W)
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