mirror of https://github.com/icedland/iced.git
240 lines
3.3 KiB
C#
240 lines
3.3 KiB
C#
/*
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Copyright (C) 2018-2019 de4dot@gmail.com
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#if !NO_DECODER
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namespace Iced.Intel.DecoderInternal {
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enum OpCodeHandlerKind : byte {
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Bitness,
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Bitness_DontReadModRM,
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Invalid,
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Invalid2,
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Dup,
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Null,
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HandlerReference,
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ArrayReference,
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RM,
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Options3,
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Options5,
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Options_DontReadModRM,
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AnotherTable,
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Group,
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Group8x64,
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Group8x8,
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MandatoryPrefix,
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MandatoryPrefix_F3_F2,
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MandatoryPrefix_MaybeModRM,
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MandatoryPrefix_NoModRM,
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MandatoryPrefix3,
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D3NOW,
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EVEX,
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VEX2,
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VEX3,
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XOP,
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AL_DX,
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Ap,
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B_BM,
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B_Ev,
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B_MIB,
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BM_B,
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BranchIw,
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BranchSimple,
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C_R_3a,
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C_R_3b,
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DX_AL,
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DX_eAX,
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eAX_DX,
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Eb_1,
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Eb_2,
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Eb_CL,
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Eb_Gb_1,
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Eb_Gb_2,
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Eb_Ib_1,
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Eb_Ib_2,
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Eb1,
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Ed_V_Ib,
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Ep,
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Ev_3a,
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Ev_3b,
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Ev_4,
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Ev_CL,
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Ev_Gv_3a,
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Ev_Gv_3b,
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Ev_Gv_4,
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Ev_Gv_32_64,
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Ev_Gv_CL,
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Ev_Gv_Ib,
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Ev_Gv_REX,
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Ev_Ib_3,
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Ev_Ib_4,
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Ev_Ib2_3,
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Ev_Ib2_4,
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Ev_Iz_3,
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Ev_Iz_4,
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Ev_P,
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Ev_REXW,
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Ev_Sw,
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Ev_VX,
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Ev1,
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Evj,
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Evw,
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Ew,
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Gb_Eb,
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Gdq_Ev,
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Gv_Eb,
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Gv_Eb_REX,
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Gv_Ev_3a,
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Gv_Ev_3b,
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Gv_Ev_32_64,
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Gv_Ev_Ib,
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Gv_Ev_Ib_REX,
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Gv_Ev_Iz,
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Gv_Ev_REX,
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Gv_Ev2,
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Gv_Ev3,
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Gv_Ew,
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Gv_M,
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Gv_M_as,
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Gv_Ma,
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Gv_Mp_2,
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Gv_Mp_3,
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Gv_Mv,
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Gv_N,
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Gv_N_Ib_REX,
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Gv_RX,
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Gv_W,
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GvM_VX_Ib,
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Ib,
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Ib3,
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IbReg,
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IbReg2,
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Iw_Ib,
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Jb,
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Jb2,
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Jdisp,
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Jx,
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Jz,
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M_1,
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M_2,
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M_REXW_2,
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M_REXW_4,
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MemBx,
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Mf_2a,
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Mf_2b,
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Mf2,
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Mf32,
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Mf64,
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Mf80,
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Mfbcd,
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Mfi16,
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Mfi32,
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Mfi64,
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MIB_B,
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MP,
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Ms,
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MV,
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Mv_Gv,
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Mv_Gv_REXW,
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NIb,
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Ob_Reg,
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Ov_Reg,
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P_Ev,
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P_Ev_Ib,
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P_Q,
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P_Q_Ib,
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P_R,
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P_W,
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PushEv,
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PushIb2,
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PushIz,
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PushOpSizeReg_4a,
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PushOpSizeReg_4b,
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PushSimple2,
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PushSimpleReg,
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Q_P,
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R_C_3a,
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R_C_3b,
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rDI_P_N,
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rDI_VX_RX,
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Reg,
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Reg_Ib2,
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Reg_Iz,
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Reg_Ob,
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Reg_Ov,
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Reg_Xb,
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Reg_Xv,
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Reg_Xv2,
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Reg_Yb,
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Reg_Yv,
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RegIb,
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RegIb3,
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RegIz2,
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ReservedNop,
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RIb,
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RIbIb,
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Rv,
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Rv_32_64,
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RvMw_Gw,
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Simple,
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Simple_ModRM,
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Simple2_3a,
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Simple2_3b,
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Simple2Iw,
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Simple3,
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Simple4,
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Simple5,
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Simple5_ModRM_as,
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SimpleReg,
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ST_STi,
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STi,
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STi_ST,
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Sw_Ev,
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V_Ev,
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VM,
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VN,
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VQ,
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VRIbIb,
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VW_2,
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VW_3,
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VWIb_2,
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VWIb_3,
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VX_E_Ib,
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VX_Ev,
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WV,
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Xb_Yb,
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Xchg_Reg_rAX,
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Xv_Yv,
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Yb_Reg,
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Yb_Xb,
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Yv_Reg,
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Yv_Reg2,
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Yv_Xv,
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}
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}
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#endif
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