mirror of https://github.com/icedland/iced.git
687 lines
13 KiB
C#
687 lines
13 KiB
C#
/*
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Copyright (C) 2018-2019 de4dot@gmail.com
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#if !NO_INSTR_INFO
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namespace Iced.Intel {
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/// <summary>
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/// CPUID feature flags
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/// </summary>
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public enum CpuidFeature {
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/// <summary>
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/// 8086 or later
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/// </summary>
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INTEL8086,
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/// <summary>
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/// 8086 only
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/// </summary>
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INTEL8086_ONLY,
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/// <summary>
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/// 80186 or later
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/// </summary>
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INTEL186,
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/// <summary>
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/// 80286 or later
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/// </summary>
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INTEL286,
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/// <summary>
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/// 80286 only
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/// </summary>
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INTEL286_ONLY,
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/// <summary>
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/// 80386 or later
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/// </summary>
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INTEL386,
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/// <summary>
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/// 80386 only
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/// </summary>
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INTEL386_ONLY,
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/// <summary>
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/// 80386 A0-B0 stepping only (xbts, ibts instructions)
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/// </summary>
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INTEL386_A0_ONLY,
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/// <summary>
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/// Intel486 or later
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/// </summary>
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INTEL486,
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/// <summary>
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/// Intel486 A stepping only (cmpxchg)
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/// </summary>
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INTEL486_A_ONLY,
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/// <summary>
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/// 80386 and Intel486 only
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/// </summary>
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INTEL386_486_ONLY,
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/// <summary>
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/// IA-64
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/// </summary>
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IA64,
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/// <summary>
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/// CPUID.80000001H:EDX.LM[bit 29]
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/// </summary>
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X64,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19]
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/// </summary>
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ADX,
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/// <summary>
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/// CPUID.01H:ECX.AES[bit 25]
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/// </summary>
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AES,
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/// <summary>
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/// CPUID.01H:ECX.AVX[bit 28]
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/// </summary>
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AVX,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]
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/// </summary>
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AVX2,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4FMAPS[bit 3]
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/// </summary>
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AVX512_4FMAPS,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4VNNIW[bit 2]
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/// </summary>
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AVX512_4VNNIW,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=1):EAX[bit 5]
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/// </summary>
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AVX512_BF16,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_BITALG[bit 12]
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/// </summary>
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AVX512_BITALG,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512_IFMA[bit 21]
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/// </summary>
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AVX512_IFMA,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI[bit 1]
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/// </summary>
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AVX512_VBMI,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI2[bit 6]
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/// </summary>
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AVX512_VBMI2,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VNNI[bit 11]
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/// </summary>
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AVX512_VNNI,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0):EDX[bit 08]
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/// </summary>
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AVX512_VP2INTERSECT,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VPOPCNTDQ[bit 14]
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/// </summary>
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AVX512_VPOPCNTDQ,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512BW[bit 30]
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/// </summary>
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AVX512BW,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512CD[bit 28]
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/// </summary>
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AVX512CD,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512DQ[bit 17]
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/// </summary>
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AVX512DQ,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512ER[bit 27]
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/// </summary>
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AVX512ER,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512F[bit 16]
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/// </summary>
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AVX512F,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512PF[bit 26]
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/// </summary>
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AVX512PF,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.AVX512VL[bit 31]
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/// </summary>
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AVX512VL,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]
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/// </summary>
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BMI1,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]
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/// </summary>
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BMI2,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EDX.CET_IBT[bit 20]
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/// </summary>
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CET_IBT,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.CET_SS[bit 7]
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/// </summary>
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CET_SS,
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/// <summary>
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/// CFLSH instruction (never implemented)
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/// </summary>
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CFLSH,
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/// <summary>
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/// CL1INVMB instruction (Intel SCC = Single-Chip Computer)
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/// </summary>
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CL1INVMB,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.CLDEMOTE[bit 25]
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/// </summary>
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CLDEMOTE,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.CLFLUSHOPT[bit 23]
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/// </summary>
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CLFLUSHOPT,
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/// <summary>
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/// CPUID.01H:EDX.CLFSH[bit 19]
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/// </summary>
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CLFSH,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24]
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/// </summary>
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CLWB,
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/// <summary>
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/// CPUID.80000008H:EBX.CLZERO[bit 0]
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/// </summary>
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CLZERO,
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/// <summary>
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/// CPUID.01H:EDX.CMOV[bit 15]
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/// </summary>
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CMOV,
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/// <summary>
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/// CPUID.01H:ECX.CMPXCHG16B[bit 13]
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/// </summary>
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CMPXCHG16B,
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/// <summary>
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/// RFLAGS.ID can be toggled
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/// </summary>
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CPUID,
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/// <summary>
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/// CPUID.01H:EDX.CX8[bit 8]
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/// </summary>
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CX8,
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/// <summary>
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/// CPUID.80000001H:EDX.3DNOW[bit 31]
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/// </summary>
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D3NOW,
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/// <summary>
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/// CPUID.80000001H:EDX.3DNOWEXT[bit 30]
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/// </summary>
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D3NOWEXT,
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/// <summary>
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/// Never implemented: CPUID.01H:EDX.ECR[bit 11]
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/// </summary>
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ECR,
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/// <summary>
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/// CPUID.(EAX=12H, ECX=0H):EAX.OSS[bit 5]
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/// </summary>
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ENCLV,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0):ECX[bit 29]
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/// </summary>
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ENQCMD,
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/// <summary>
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/// CPUID.01H:ECX.F16C[bit 29]
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/// </summary>
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F16C,
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/// <summary>
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/// CPUID.01H:ECX.FMA[bit 12]
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/// </summary>
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FMA,
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/// <summary>
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/// CPUID.80000001H:ECX.FMA4[bit 16]
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/// </summary>
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FMA4,
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/// <summary>
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/// 8087 or later (CPUID.01H:EDX.FPU[bit 0])
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/// </summary>
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FPU,
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/// <summary>
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/// 80287 or later
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/// </summary>
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FPU287,
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/// <summary>
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/// 80287XL only
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/// </summary>
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FPU287XL_ONLY,
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/// <summary>
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/// 80387 or later
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/// </summary>
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FPU387,
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/// <summary>
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/// 80387SL only
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/// </summary>
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FPU387SL_ONLY,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.FSGSBASE[bit 0]
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/// </summary>
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FSGSBASE,
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/// <summary>
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/// CPUID.01H:EDX.FXSR[bit 24]
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/// </summary>
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FXSR,
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/// <summary>
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/// AMD Geode LX/GX CPU
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/// </summary>
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GEODE,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.GFNI[bit 8]
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/// </summary>
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GFNI,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.HLE[bit 4]
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/// </summary>
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HLE,
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/// <summary>
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/// <see cref="HLE"/> or <see cref="RTM"/>
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/// </summary>
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HLE_or_RTM,
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/// <summary>
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/// <see cref="VMX"/> and IA32_VMX_EPT_VPID_CAP[bit 20]
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/// </summary>
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INVEPT,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.INVPCID[bit 10]
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/// </summary>
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INVPCID,
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/// <summary>
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/// <see cref="VMX"/> and IA32_VMX_EPT_VPID_CAP[bit 32]
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/// </summary>
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INVVPID,
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/// <summary>
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/// CPUID.80000001H:ECX.LWP[bit 15]
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/// </summary>
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LWP,
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/// <summary>
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/// CPUID.80000001H:ECX.LZCNT[bit 5]
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/// </summary>
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LZCNT,
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/// <summary>
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/// CPUID.01H:EDX.MMX[bit 23]
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/// </summary>
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MMX,
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/// <summary>
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/// CPUID.01H:ECX.MONITOR[bit 3]
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/// </summary>
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MONITOR,
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/// <summary>
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/// CPUID.80000001H:ECX.MONITORX[bit 29]
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/// </summary>
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MONITORX,
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/// <summary>
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/// CPUID.01H:ECX.MOVBE[bit 22]
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/// </summary>
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MOVBE,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.MOVDIR64B[bit 28]
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/// </summary>
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MOVDIR64B,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.MOVDIRI[bit 27]
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/// </summary>
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MOVDIRI,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.MPX[bit 14]
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/// </summary>
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MPX,
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/// <summary>
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/// CPUID.01H:EDX.MSR[bit 5]
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/// </summary>
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MSR,
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/// <summary>
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/// Multi-byte nops (0F1F /0): CPUID.01H.EAX[Bits 11:8] = 0110B or 1111B
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/// </summary>
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MULTIBYTENOP,
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/// <summary>
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/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.ACE[Bits 7:6] = 11B ([6] = exists, [7] = enabled)
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/// </summary>
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PADLOCK_ACE,
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/// <summary>
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/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PHE[Bits 11:10] = 11B ([10] = exists, [11] = enabled)
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/// </summary>
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PADLOCK_PHE,
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/// <summary>
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/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PMM[Bits 13:12] = 11B ([12] = exists, [13] = enabled)
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/// </summary>
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PADLOCK_PMM,
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/// <summary>
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/// CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.RNG[Bits 3:2] = 11B ([2] = exists, [3] = enabled)
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/// </summary>
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PADLOCK_RNG,
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/// <summary>
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/// PAUSE instruction (Pentium 4 or later)
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/// </summary>
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PAUSE,
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/// <summary>
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/// CPUID.01H:ECX.PCLMULQDQ[bit 1]
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/// </summary>
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PCLMULQDQ,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.PCOMMIT[bit 22]
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/// </summary>
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PCOMMIT,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EDX.PCONFIG[bit 18]
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/// </summary>
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PCONFIG,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.PKU[bit 3]
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/// </summary>
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PKU,
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/// <summary>
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/// CPUID.01H:ECX.POPCNT[bit 23]
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/// </summary>
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POPCNT,
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/// <summary>
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/// CPUID.80000001H:ECX.PREFETCHW[bit 8]
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/// </summary>
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PREFETCHW,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.PREFETCHWT1[bit 0]
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/// </summary>
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PREFETCHWT1,
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/// <summary>
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/// CPUID.(EAX=14H, ECX=0H):EBX.PTWRITE[bit 4]
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/// </summary>
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PTWRITE,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):ECX.RDPID[bit 22]
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/// </summary>
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RDPID,
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/// <summary>
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/// RDPMC instruction (Pentium MMX or later, or Pentium Pro or later)
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/// </summary>
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RDPMC,
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/// <summary>
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/// CPUID.01H:ECX.RDRAND[bit 30]
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/// </summary>
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RDRAND,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]
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/// </summary>
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RDSEED,
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/// <summary>
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/// CPUID.80000001H:EDX.RDTSCP[bit 27]
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/// </summary>
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RDTSCP,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.RTM[bit 11]
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/// </summary>
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RTM,
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/// <summary>
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/// CPUID.01H:EDX.SEP[bit 11]
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/// </summary>
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SEP,
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/// <summary>
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/// CPUID.(EAX=12H, ECX=0H):EAX.SGX1[bit 0]
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/// </summary>
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SGX1,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.SHA[bit 29]
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/// </summary>
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SHA,
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/// <summary>
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/// CPUID.80000001H:ECX.SKINIT[bit 12]
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/// </summary>
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SKINIT,
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/// <summary>
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/// <see cref="SKINIT"/> or <see cref="SVML"/>
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/// </summary>
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SKINIT_or_SVML,
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/// <summary>
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/// CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20]
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|
/// </summary>
|
|
SMAP,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.SMX[bit 6]
|
|
/// </summary>
|
|
SMX,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:EDX.SSE[bit 25]
|
|
/// </summary>
|
|
SSE,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:EDX.SSE2[bit 26]
|
|
/// </summary>
|
|
SSE2,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.SSE3[bit 0]
|
|
/// </summary>
|
|
SSE3,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.SSE4_1[bit 19]
|
|
/// </summary>
|
|
SSE4_1,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.SSE4_2[bit 20]
|
|
/// </summary>
|
|
SSE4_2,
|
|
|
|
/// <summary>
|
|
/// CPUID.80000001H:ECX.SSE4A[bit 6]
|
|
/// </summary>
|
|
SSE4A,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.SSSE3[bit 9]
|
|
/// </summary>
|
|
SSSE3,
|
|
|
|
/// <summary>
|
|
/// CPUID.80000001H:ECX.SVM[bit 2]
|
|
/// </summary>
|
|
SVM,
|
|
|
|
/// <summary>
|
|
/// CPUID.8000000AH:EDX.SVML[bit 2]
|
|
/// </summary>
|
|
SVML,
|
|
|
|
/// <summary>
|
|
/// CPUID.80000001H:EDX.SYSCALL[bit 11]
|
|
/// </summary>
|
|
SYSCALL,
|
|
|
|
/// <summary>
|
|
/// CPUID.80000001H:ECX.TBM[bit 21]
|
|
/// </summary>
|
|
TBM,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:EDX.TSC[bit 4]
|
|
/// </summary>
|
|
TSC,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=07H, ECX=0H):ECX.VAES[bit 9]
|
|
/// </summary>
|
|
VAES,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.VMX[bit 5]
|
|
/// </summary>
|
|
VMX,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=07H, ECX=0H):ECX.VPCLMULQDQ[bit 10]
|
|
/// </summary>
|
|
VPCLMULQDQ,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=07H, ECX=0H):ECX.WAITPKG[bit 5]
|
|
/// </summary>
|
|
WAITPKG,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=80000008H, ECX=0H):EBX.WBNOINVD[bit 9]
|
|
/// </summary>
|
|
WBNOINVD,
|
|
|
|
/// <summary>
|
|
/// CPUID.80000001H:ECX.XOP[bit 11]
|
|
/// </summary>
|
|
XOP,
|
|
|
|
/// <summary>
|
|
/// CPUID.01H:ECX.XSAVE[bit 26]
|
|
/// </summary>
|
|
XSAVE,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEC[bit 1]
|
|
/// </summary>
|
|
XSAVEC,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEOPT[bit 0]
|
|
/// </summary>
|
|
XSAVEOPT,
|
|
|
|
/// <summary>
|
|
/// CPUID.(EAX=0DH, ECX=1H):EAX.XSAVES[bit 3]
|
|
/// </summary>
|
|
XSAVES,
|
|
|
|
/// <summary>
|
|
/// Never implemented: CPUID.01H:EDX.ZALLOC[bit 16]
|
|
/// </summary>
|
|
ZALLOC,
|
|
}
|
|
}
|
|
#endif
|