mirror of https://github.com/icedland/iced.git
145 lines
4.0 KiB
C#
145 lines
4.0 KiB
C#
/*
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Copyright (C) 2018-2019 de4dot@gmail.com
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#if (!NO_DECODER32 || !NO_DECODER64) && !NO_DECODER
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using System;
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namespace Iced.Intel {
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/// <summary>
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/// Decoder options
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/// </summary>
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[Flags]
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public enum DecoderOptions : uint {
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/// <summary>
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/// No option is enabled
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/// </summary>
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None = 0,
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/// <summary>
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/// AMD decoder: allow 16-bit branch/ret instructions in 64-bit mode
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/// </summary>
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AMD = 0x00000001,
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/// <summary>
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/// Decode opcodes 0F0D and 0F18-0F1F as reserved-nop instructions (eg. <see cref="Code.ReservedNop_rm32_r32_0F1D"/>)
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/// </summary>
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ForceReservedNop = 0x00000002,
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/// <summary>
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/// Decode <see cref="Code.Cflsh"/>
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/// </summary>
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Cflsh = 0x00000004,
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/// <summary>
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/// Decode umov instructions (eg. <see cref="Code.Umov_r32_rm32"/>)
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/// </summary>
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Umov = 0x00000008,
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/// <summary>
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/// Decode <see cref="Code.Rdecr"/> and <see cref="Code.Wrecr"/>
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/// </summary>
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Ecr = 0x00000010,
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/// <summary>
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/// Decode xbts/ibts
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/// </summary>
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Xbts = 0x00000020,
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/// <summary>
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/// Decode 0FA6/0FA7 as cmpxchg
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/// </summary>
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Cmpxchg486A = 0x00000040,
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/// <summary>
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/// Decode <see cref="Code.Zalloc_m256"/>
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/// </summary>
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Zalloc = 0x00000080,
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/// <summary>
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/// Decode some old removed FPU instructions (eg. frstpm)
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/// </summary>
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OldFpu = 0x00000100,
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/// <summary>
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/// Decode <see cref="Code.Pcommit"/>
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/// </summary>
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Pcommit = 0x00000200,
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/// <summary>
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/// Decode 286 loadall (0F04 and 0F05)
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/// </summary>
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Loadall286 = 0x00000400,
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/// <summary>
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/// Decode <see cref="Code.Loadall386"/>
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/// </summary>
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Loadall386 = 0x00000800,
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/// <summary>
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/// Decode <see cref="Code.Cl1invmb"/>
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/// </summary>
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Cl1invmb = 0x00001000,
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/// <summary>
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/// Decode <see cref="Code.Mov_r32_tr"/> and <see cref="Code.Mov_tr_r32"/>
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/// </summary>
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MovTr = 0x00002000,
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/// <summary>
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/// Don't decode <see cref="Code.Pause"/>, decode <see cref="Code.Nopd"/>/etc instead
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/// </summary>
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NoPause = 0x00004000,
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/// <summary>
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/// Don't decode <see cref="Code.Wbnoinvd"/>, decode <see cref="Code.Wbinvd"/> instead
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/// </summary>
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NoWbnoinvd = 0x00008000,
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/// <summary>
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/// Don't decode LOCK MOV CR0 as MOV CR8
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/// </summary>
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NoLockMovCR0 = 0x00010000,
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/// <summary>
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/// Don't decode <see cref="Code.Popcnt_r32_rm32"/>/etc, decode eg. <see cref="Code.Jmpe_disp32"/>/etc instead
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/// </summary>
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NoMPFX_0FB8 = 0x00020000,
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/// <summary>
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/// Don't decode <see cref="Code.Tzcnt_r32_rm32"/>/etc, decode <see cref="Code.Bsf_r32_rm32"/>/etc instead
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/// </summary>
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NoMPFX_0FBC = 0x00040000,
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/// <summary>
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/// Don't decode <see cref="Code.Lzcnt_r32_rm32"/>/etc, decode <see cref="Code.Bsr_r32_rm32"/>/etc instead
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/// </summary>
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NoMPFX_0FBD = 0x00080000,
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/// <summary>
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/// Don't decode <see cref="Code.Lahf"/> and <see cref="Code.Sahf"/> in 64-bit mode
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/// </summary>
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NoLahfSahf64 = 0x00100000,
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}
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}
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#endif
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