mirror of https://github.com/icedland/iced.git
90 lines
3.7 KiB
C#
90 lines
3.7 KiB
C#
/*
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Copyright (C) 2018-2019 de4dot@gmail.com
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#if !NO_DECODER32 && !NO_DECODER
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using System.Diagnostics;
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using System.Runtime.CompilerServices;
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namespace Iced.Intel {
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sealed partial class Decoder {
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal void ReadOpMem_m32(ref Instruction instruction) {
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Debug.Assert(!is64Mode);
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Debug.Assert(state.addressSize == OpSize.Size16 || state.addressSize == OpSize.Size32);
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Debug.Assert(state.Encoding != EncodingKind.EVEX);
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if (state.addressSize == OpSize.Size32)
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ReadOpMem32Or64(ref instruction, Register.EAX, Register.EAX, TupleType.None, false);
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else
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ReadOpMem16(ref instruction, TupleType.None);
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}
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// All MPX instructions in 16/32-bit mode require 32-bit addressing (see SDM Vol 1, 17.5.1 Intel MPX and Operating Modes)
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal void ReadOpMem_m32_ONLY32(ref Instruction instruction) {
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Debug.Assert(!is64Mode);
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Debug.Assert(state.addressSize == OpSize.Size16 || state.addressSize == OpSize.Size32);
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Debug.Assert(state.Encoding != EncodingKind.EVEX);
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if (state.addressSize == OpSize.Size32)
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ReadOpMem32Or64(ref instruction, Register.EAX, Register.EAX, TupleType.None, false);
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else
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SetInvalidInstruction();
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal void ReadOpMem_m32(ref Instruction instruction, TupleType tupleType) {
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Debug.Assert(!is64Mode);
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Debug.Assert(state.addressSize == OpSize.Size16 || state.addressSize == OpSize.Size32);
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if (state.addressSize == OpSize.Size32)
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ReadOpMem32Or64(ref instruction, Register.EAX, Register.EAX, tupleType, false);
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else
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ReadOpMem16(ref instruction, tupleType);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal void ReadOpMem_VSIB_m32(ref Instruction instruction, Register vsibIndex) {
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Debug.Assert(!is64Mode);
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Debug.Assert(state.addressSize == OpSize.Size16 || state.addressSize == OpSize.Size32);
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Debug.Assert(state.Encoding != EncodingKind.EVEX);
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if (state.addressSize == OpSize.Size32) {
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if (!ReadOpMem32Or64(ref instruction, Register.EAX, vsibIndex, TupleType.None, true))
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SetInvalidInstruction();
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}
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else
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SetInvalidInstruction();
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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internal void ReadOpMem_VSIB_m32(ref Instruction instruction, Register vsibIndex, TupleType tupleType) {
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Debug.Assert(!is64Mode);
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Debug.Assert(state.addressSize == OpSize.Size16 || state.addressSize == OpSize.Size32);
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if (state.addressSize == OpSize.Size32) {
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if (!ReadOpMem32Or64(ref instruction, Register.EAX, vsibIndex, tupleType, true))
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SetInvalidInstruction();
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}
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else
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SetInvalidInstruction();
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}
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}
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}
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#endif
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