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102 Commits 10 Branches 33 Tags 106 MiB
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56 Commits

Author SHA1 Message Date
de4dot 3e10b1af17 Add TryEncode() 2018-09-19 19:49:50 +02:00
de4dot e9fce2f6a0 Add Instruction.Create() methods 2018-09-18 23:38:51 +02:00
de4dot 03877b65fb Decoder handlers use new internal props to write to reg fields 2018-09-18 23:38:39 +02:00
de4dot 96744c75ad Make Instruction.OpCount read only, fixes #19 2018-09-17 22:48:14 +02:00
de4dot ebc8fb103f Rename 2018-09-17 21:03:29 +02:00
de4dot b5344acd43 Rename fxsave/fxrstor 2018-09-17 21:00:53 +02:00
de4dot bfc5f296a5 Rename Xbegin REX.W Code value 2018-09-17 20:06:31 +02:00
de4dot fd61680f52 Rename Code values 2018-09-17 19:49:26 +02:00
de4dot e49702a43d Fix memory size value 2018-09-17 19:19:29 +02:00
de4dot 72f1d05fdd Update encoder table: call/jmp far mem only support mem ops 2018-09-17 19:19:15 +02:00
de4dot 64125de948 Ignore es,cs,ss,ds in 64-bit mode if they're used by a mem op 2018-09-15 12:38:43 +02:00
de4dot 4ae55dd41b Add instruction info (AMD Instructions) 2018-09-14 22:21:54 +02:00
de4dot ae0d29c7c6 Add pseudo ops tests 2018-09-14 22:21:46 +02:00
de4dot e4db0bd533 Add more tests 2018-09-14 22:21:38 +02:00
de4dot 5c6a0f45f7 Update formatters (AMD instructions) 2018-09-13 21:48:23 +02:00
de4dot eff433e656 Update comment 2018-09-13 21:48:07 +02:00
de4dot 7eb8e71c1d Merge branch 'master' into amd 2018-09-13 07:35:26 +02:00
de4dot bd7d965d99 Pass in size of imm to SymbolResolver methods, fixes #13 2018-09-13 07:31:30 +02:00
de4dot 4d1289f42a Fix opcode comments 2018-09-12 23:34:20 +02:00
de4dot 4e039571b8 Remove unused values 2018-09-12 23:32:56 +02:00
de4dot b353271cc3 Update encoder tables (AMD instructions) 2018-09-12 20:47:19 +02:00
de4dot 57c73fae6d Add instruction tests (AMD instructions) 2018-09-12 20:47:02 +02:00
de4dot cf837cb71a Update decoder tables (AMD instructions) 2018-09-11 01:06:40 +02:00
de4dot e9cf5b080b Move and rename Code values 2018-09-11 01:06:23 +02:00
de4dot 72406c934d Rename 2nd imm opkind 2018-09-11 01:06:13 +02:00
de4dot 67ae532242 Rename 2018-09-11 01:05:58 +02:00
de4dot df3597b0ed Add a 5th operand 2018-09-11 01:05:03 +02:00
de4dot 0a7158a046 Add XOP / 3DNow encodings 2018-09-11 01:04:55 +02:00
de4dot 6126f34114 Add crc32 (word) tests 2018-09-09 13:31:20 +02:00
de4dot 585a1b3e66 Update tables so the code compiles 2018-09-09 13:31:11 +02:00
de4dot 2601009b8b Increment Code value bit length to 13 bits 2018-09-09 13:31:03 +02:00
de4dot 975b0f5c95 Add AMD Code values from vol 5 2018-09-09 13:30:54 +02:00
de4dot 270ebb4553 Add AMD Code values from vol 4 2018-09-09 13:30:46 +02:00
de4dot 4eca090ff5 Add AMD Code values from vol 3 2018-09-09 13:30:38 +02:00
de4dot 4f73eeb959 Add a CanReadByte prop 2018-09-07 21:09:18 +02:00
de4dot d2978e2eaf Add missing setcc [mem] tests 2018-09-07 21:08:37 +02:00
de4dot 2163ea629a Remove flags field and add access + scale fields 2018-09-07 21:08:28 +02:00
de4dot f86f48820c Move instr info tests to instr info sub dir 2018-09-07 21:08:15 +02:00
de4dot babd1b45ab Show unused seg override 2018-09-07 21:08:05 +02:00
de4dot e24a90c508 Add rsm fw=all 2018-09-07 21:07:45 +02:00
de4dot 2c728a62c2 Rename opmask props 2018-09-07 21:07:27 +02:00
de4dot 388477fc4e Change MemoryIndexScale value from 0-3 to 1,2,4,8 2018-09-07 21:07:17 +02:00
de4dot a154fd18cf Update masm + loop/loopcc output 2018-09-07 21:07:05 +02:00
de4dot d9ad7b537d Add 64-bit versions of {v,}pcmpestr[mi] 2018-09-07 21:06:51 +02:00
de4dot 5795a9a01d Fix comments 2018-09-07 21:06:41 +02:00
de4dot 1c73687139 Add 32-bit arpl 2018-09-07 21:06:33 +02:00
de4dot 87e146b78e Rename some Code values 2018-09-07 21:06:25 +02:00
de4dot cdc27ee491 Assume iretw=16-bit / iretd=32-bit if CodeSize is unknown 2018-09-07 21:06:06 +02:00
de4dot 9894cfcc57 Update leave handler to add one less reg if possible 2018-09-06 20:57:09 +02:00
de4dot 236ff788e5 Add missing [Flags] attribute 2018-09-06 20:57:00 +02:00