Rooba
/
iced
mirror of https://github.com/icedland/iced.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
346 Commits 10 Branches 33 Tags 106 MiB
Commit Graph

45 Commits

Author SHA1 Message Date
de4dot 689cbd3934 Add net452 and net35 tfs 2019-02-15 19:58:18 +01:00
de4dot fcf973a24c Obsolete CpuidFeature prop and add CpuidFeatures prop 2019-02-12 22:03:26 +01:00
de4dot 26895cb81c Update CPUID feature value 2019-02-06 19:08:19 +01:00
de4dot e870c5a903 Remove Xbegin_rel32_REXW 2019-01-06 22:39:59 +01:00
de4dot d893407290 Remove padlock operand, create more Code values 2019-01-02 16:29:25 +01:00
de4dot 5d95b1bf37 Add VIA padlock instructions 2019-01-02 01:17:43 +01:00
de4dot c667fe9265 Change license from LGPL3+ to MIT, closes #34 2019-01-01 13:40:59 +01:00
de4dot 220f944b0d Remove utf8 bom 2019-01-01 12:53:32 +01:00
de4dot 0a7bbfc2a1 Update copyright years 2019-01-01 12:10:41 +01:00
de4dot 708508ec01 Add a new AVX->AVX2 check flag 2018-12-23 15:06:39 +01:00
de4dot a3bd5a5fb7 Update bndldx/bndstx, seg override can be used 2018-12-23 15:05:48 +01:00
de4dot 9b2734c77c Update FCOMI CPUID feature bits, it's bits 15 and 0 according to Intel manual 2018-10-26 22:22:05 +02:00
de4dot 32a86ccc26 Support xor/sub reg,reg since reg is written only, not read 2018-10-24 21:23:59 +02:00
de4dot 83b43ee79c AMD CPUs support syscall/sysret in 32-bit mode 2018-10-07 22:32:26 +02:00
de4dot 3f18b0813f Sort 2018-10-07 22:32:18 +02:00
de4dot 5be76ac4bd Sort 2018-09-30 12:34:27 +02:00
de4dot 32e1833156 Add instruction info tests 2018-09-28 22:45:16 +02:00
de4dot 7c5008a4fa Support 16-bit branches/ret in 64-bit mode 2018-09-25 21:25:54 +02:00
de4dot 5f9e9545fb Rename 2018-09-24 23:54:37 +02:00
de4dot d16da72af6 Update instr info table 2018-09-24 23:54:17 +02:00
de4dot ecf824d712 Sort nop/xchg code values 2018-09-21 18:50:34 +02:00
Alexandre Mutel 4ce66e5d23 Rename Xchg to r16_AX/r32_EAX/r64_RAX 2018-09-20 14:45:04 +02:00
Alexandre Mutel 2060f132f4 Add support for Code.Bswap_r16, Bswap_r32, Bswap_r64 2018-09-20 13:06:36 +02:00
Alexandre Mutel 75f480be07 Add support for Xchg_AX_r16, Xchg_EAX_r32, Xchg_RAX_r64 2018-09-20 12:52:37 +02:00
Alexandre Mutel d579af350e Add support for Mov_r8_imm8, Mov_r16_imm16, Mov_r32_imm32, Mov_r64_imm64 2018-09-20 11:46:33 +02:00
Alexandre Mutel 8eb2cf9105 Merge remote-tracking branch 'source/master' into new-opcode-mov 
# Conflicts:
#	Iced.UnitTests/Intel/EncoderTests/EncoderTest.cs
 2018-09-20 10:25:25 +02:00
Alexandre Mutel cc16730743 Migrate instructions: Inc|Dec_r16/r32 push|pop_r16/r32/r64 2018-09-20 10:18:42 +02:00
de4dot eda091e30a Sort 2018-09-19 19:50:21 +02:00
de4dot ebc8fb103f Rename 2018-09-17 21:03:29 +02:00
de4dot b5344acd43 Rename fxsave/fxrstor 2018-09-17 21:00:53 +02:00
de4dot bfc5f296a5 Rename Xbegin REX.W Code value 2018-09-17 20:06:31 +02:00
de4dot fd61680f52 Rename Code values 2018-09-17 19:49:26 +02:00
de4dot 4ae55dd41b Add instruction info (AMD Instructions) 2018-09-14 22:21:54 +02:00
de4dot b353271cc3 Update encoder tables (AMD instructions) 2018-09-12 20:47:19 +02:00
de4dot e9cf5b080b Move and rename Code values 2018-09-11 01:06:23 +02:00
de4dot df3597b0ed Add a 5th operand 2018-09-11 01:05:03 +02:00
de4dot 0a7158a046 Add XOP / 3DNow encodings 2018-09-11 01:04:55 +02:00
de4dot 585a1b3e66 Update tables so the code compiles 2018-09-09 13:31:11 +02:00
de4dot e24a90c508 Add rsm fw=all 2018-09-07 21:07:45 +02:00
de4dot d9ad7b537d Add 64-bit versions of {v,}pcmpestr[mi] 2018-09-07 21:06:51 +02:00
de4dot 1c73687139 Add 32-bit arpl 2018-09-07 21:06:33 +02:00
de4dot 87e146b78e Rename some Code values 2018-09-07 21:06:25 +02:00
de4dot 236ff788e5 Add missing [Flags] attribute 2018-09-06 20:57:00 +02:00
de4dot 358eeb338e Rename flags props 2018-09-06 20:56:36 +02:00
de4dot e17212a64d Add instruction info files 2018-09-06 01:46:48 +02:00