Rooba
/
iced
mirror of https://github.com/icedland/iced.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update a few tests with more useless prefixes

This commit is contained in:
de4dot 2019-03-26 15:17:11 +01:00
parent d9227fb159
commit f4f3e11d09
3 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Iced.UnitTests/Intel/DecoderTests/DecoderTest16.txt
View File

@ -29,6 +29,7 @@
66 01 CE, Add_rm32_r32, 2, op0=r;esi op1=r;ecx
66 01 18, Add_rm32_r32, 2, op0=m;ds;bx;si;1;0;0;UInt32 op1=r;ebx
F0 66 67 F3 F2 01 18, Add_rm32_r32, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx lock rep xacquire
02 CE, Add_r8_rm8, 2, op0=r;cl op1=r;dh
02 38, Add_r8_rm8, 2, op0=r;bh op1=m;ds;bx;si;1;0;0;UInt8
@ -2269,7 +2270,7 @@ C5FD 10 CD, VEX_Vmovupd_ymm_ymmm256, 2, op0=r;ymm1 op1=r;ymm5
62 F1FDCB 10 D3, EVEX_Vmovupd_zmm_k1z_zmmm512, 2, op0=r;zmm2 op1=r;zmm3 k3 zmsk
F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;bx;si;1;0;0;Float32
67 F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float32
67 F2 F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float32 repne
F3 0F10 CD, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=r;xmm5
C5CA 10 CD, VEX_Vmovss_xmm_xmm_xmm, 3, op0=r;xmm1 op1=r;xmm6 op2=r;xmm5
@ -2293,7 +2294,7 @@ C4E1FE 10 10, VEX_Vmovss_xmm_m32, 2, op0=r;xmm2 op1=m;ds;bx;si;1;0;0;Float32 enc
62 F17E68 10 50 01, EVEX_Vmovss_xmm_k1z_m32, 2, op0=r;xmm2 op1=m;ds;bx;si;1;4;1;Float32 co=0;0;0;0;6;1 enc=62F17E08105001
F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;bx;si;1;0;0;Float64
67 F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float64
67 F3 F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float64 rep
F2 0F10 CD, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=r;xmm5
C5CB 10 CD, VEX_Vmovsd_xmm_xmm_xmm, 3, op0=r;xmm1 op1=r;xmm6 op2=r;xmm5

5
Iced.UnitTests/Intel/DecoderTests/DecoderTest32.txt
View File

@ -26,6 +26,7 @@
66 01 CE, Add_rm16_r16, 2, op0=r;si op1=r;cx
66 01 18, Add_rm16_r16, 2, op0=m;ds;eax;;1;0;0;UInt16 op1=r;bx
F0 66 67 F3 F2 01 18, Add_rm16_r16, 2, op0=m;ds;bx;si;1;0;0;UInt16 op1=r;bx lock rep xacquire
01 CE, Add_rm32_r32, 2, op0=r;esi op1=r;ecx
01 18, Add_rm32_r32, 2, op0=m;ds;eax;;1;0;0;UInt32 op1=r;ebx
@ -2269,7 +2270,7 @@ C5FD 10 CD, VEX_Vmovupd_ymm_ymmm256, 2, op0=r;ymm1 op1=r;ymm5
62 F1FDCB 10 D3, EVEX_Vmovupd_zmm_k1z_zmmm512, 2, op0=r;zmm2 op1=r;zmm3 k3 zmsk
F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float32
67 F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;bx;si;1;0;0;Float32
67 F2 F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;bx;si;1;0;0;Float32 repne
F3 0F10 CD, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=r;xmm5
C5CA 10 CD, VEX_Vmovss_xmm_xmm_xmm, 3, op0=r;xmm1 op1=r;xmm6 op2=r;xmm5
@ -2290,7 +2291,7 @@ C4E1FE 10 10, VEX_Vmovss_xmm_m32, 2, op0=r;xmm2 op1=m;ds;eax;;1;0;0;Float32 enc=
62 F17E8B 10 50 01, EVEX_Vmovss_xmm_k1z_m32, 2, op0=r;xmm2 op1=m;ds;eax;;1;4;1;Float32 k3 zmsk co=0;0;0;0;6;1
F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float64
67 F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;bx;si;1;0;0;Float64
67 F3 F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;bx;si;1;0;0;Float64 rep
F2 0F10 CD, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=r;xmm5
C5CB 10 CD, VEX_Vmovsd_xmm_xmm_xmm, 3, op0=r;xmm1 op1=r;xmm6 op2=r;xmm5

5
Iced.UnitTests/Intel/DecoderTests/DecoderTest64.txt
View File

@ -48,6 +48,7 @@ F2 48 0FB8 CE, INVALID, 0, nompfx_0fb8
66 41 01 D9, Add_rm16_r16, 2, op0=r;r9w op1=r;bx
66 44 01 EC, Add_rm16_r16, 2, op0=r;sp op1=r;r13w
66 01 18, Add_rm16_r16, 2, op0=m;ds;rax;;1;0;0;UInt16 op1=r;bx
F0 66 67 F3 F2 01 18, Add_rm16_r16, 2, op0=m;ds;eax;;1;0;0;UInt16 op1=r;bx lock rep xacquire
01 CE, Add_rm32_r32, 2, op0=r;esi op1=r;ecx
44 01 C5, Add_rm32_r32, 2, op0=r;ebp op1=r;r8d
@ -4208,7 +4209,7 @@ C4417D 10 CD, VEX_Vmovupd_ymm_ymmm256, 2, op0=r;ymm9 op1=r;ymm13
62 C1FDCB 10 D3, EVEX_Vmovupd_zmm_k1z_zmmm512, 2, op0=r;zmm18 op1=r;zmm11 k3 zmsk
F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;rax;;1;0;0;Float32
67 F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float32
67 F2 F3 0F10 08, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float32 repne
F3 0F10 CD, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=r;xmm5
F3 44 0F10 CD, Movss_xmm_xmmm32, 2, op0=r;xmm9 op1=r;xmm5
F3 41 0F10 CD, Movss_xmm_xmmm32, 2, op0=r;xmm1 op1=r;xmm13
@ -4239,7 +4240,7 @@ C4E1FE 10 10, VEX_Vmovss_xmm_m32, 2, op0=r;xmm2 op1=m;ds;rax;;1;0;0;Float32 enc=
62 F17E8B 10 50 01, EVEX_Vmovss_xmm_k1z_m32, 2, op0=r;xmm2 op1=m;ds;rax;;1;4;1;Float32 k3 zmsk co=0;0;0;0;6;1
F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;rax;;1;0;0;Float64
67 F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float64
67 F3 F2 0F10 08, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=m;ds;eax;;1;0;0;Float64 rep
F2 0F10 CD, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=r;xmm5
F2 44 0F10 CD, Movsd_xmm_xmmm64, 2, op0=r;xmm9 op1=r;xmm5
F2 41 0F10 CD, Movsd_xmm_xmmm64, 2, op0=r;xmm1 op1=r;xmm13