diff --git a/src/csharp/Intel/Generator/Tables/InstructionDef.cs b/src/csharp/Intel/Generator/Tables/InstructionDef.cs
index d376b89a0..d42316de1 100644
--- a/src/csharp/Intel/Generator/Tables/InstructionDef.cs
+++ b/src/csharp/Intel/Generator/Tables/InstructionDef.cs
@@ -377,6 +377,10 @@ namespace Generator.Tables {
/// The index register is ignored when calculating the effective address (eg. BNDLDX, BNDSTX)
///
IgnoresIndex = 0x00040000,//TODO: Add to OpCodeInfo
+ ///
+ /// The index register (if present) is the tile stride indicator
+ ///
+ TileStrideIndex = 0x00080000,//TODO: Add to OpCodeInfo
}
enum VmxMode {
diff --git a/src/csharp/Intel/Generator/Tables/InstructionDefs.txt b/src/csharp/Intel/Generator/Tables/InstructionDefs.txt
index 60115ed5f..70c2e7a47 100644
--- a/src/csharp/Intel/Generator/Tables/InstructionDefs.txt
+++ b/src/csharp/Intel/Generator/Tables/InstructionDefs.txt
@@ -29634,19 +29634,19 @@ END
# Code: VEX_Tileloaddt1_tmm_sibmem
INSTRUCTION: VEX.128.66.0F38.W0 4B !(11):rrr:100 | TILELOADDT1 tmm1, sibmem | AMX_TILE
ops: w=tmm_reg r=sibmem | Tile
- flags: 64 tsx-abort
+ flags: 64 tile-stride-index tsx-abort
END
# Code: VEX_Tilestored_sibmem_tmm
INSTRUCTION: VEX.128.F3.0F38.W0 4B !(11):rrr:100 | TILESTORED sibmem, tmm1 | AMX_TILE
ops: w=sibmem r=tmm_reg | Tile
- flags: 64 tsx-abort
+ flags: 64 tile-stride-index tsx-abort
END
# Code: VEX_Tileloadd_tmm_sibmem
INSTRUCTION: VEX.128.F2.0F38.W0 4B !(11):rrr:100 | TILELOADD tmm1, sibmem | AMX_TILE
ops: w=tmm_reg r=sibmem | Tile
- flags: 64 tsx-abort
+ flags: 64 tile-stride-index tsx-abort
END
# Code: VEX_Tdpbf16ps_tmm_tmm_tmm
diff --git a/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs b/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs
index a48b2a0b8..74805521a 100644
--- a/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs
+++ b/src/csharp/Intel/Generator/Tables/InstructionDefsReader.cs
@@ -548,6 +548,7 @@ namespace Generator.Tables {
case "k-elem-selector": state.Flags3 |= InstructionDefFlags3.OpMaskIsElementSelector; break;
case "prefetch": state.Flags3 |= InstructionDefFlags3.Prefetch; break;
case "ignores-index": state.Flags3 |= InstructionDefFlags3.IgnoresIndex; break;
+ case "tile-stride-index": state.Flags3 |= InstructionDefFlags3.TileStrideIndex; break;
case "vmx=op":
case "vmx=root":