diff --git a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
index baa94030d..2585c5d63 100644
--- a/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
+++ b/src/UnitTests/Intel/InstructionInfo/InstructionInfoTest_64.txt
@@ -19159,10 +19159,16 @@ C4E279 49 00, VEX_Sttilecfg_m512, VEX, AMX_TILE, op0=w r=rax wm=ds:rax;Tilecfg
 C4E27B 49 D0, VEX_Tilezero_tmm, VEX, AMX_TILE, op0=w w=tmm2
 # tileloaddt1 tmm2,[rcx+rdx*4]
 C4E279 4B 14 91, VEX_Tileloaddt1_tmm_sibmem, VEX, AMX_TILE, op0=w op1=r w=tmm2 r=rcx;rdx rm=ds:rcx;Tile
+# tileloaddt1 tmm6,[rdx-5AA5EDCCh]
+C4E279 4B B4 22 34125AA5, VEX_Tileloaddt1_tmm_sibmem, VEX, AMX_TILE, op0=w op1=r w=tmm6 r=rdx rm=ds:rdx+0xFFFFFFFFA55A1234;Tile
 # tilestored [rcx+rdx*4],tmm2
 C4E27A 4B 14 91, VEX_Tilestored_sibmem_tmm, VEX, AMX_TILE, op0=w op1=r r=tmm2;rcx;rdx wm=ds:rcx;Tile
+# tilestored [rdx-5AA5EDCCh],tmm6
+C4E27A 4B B4 22 34125AA5, VEX_Tilestored_sibmem_tmm, VEX, AMX_TILE, op0=w op1=r r=tmm6;rdx wm=ds:rdx+0xFFFFFFFFA55A1234;Tile
 # tileloadd tmm2,[rcx+rdx*4]
 C4E27B 4B 14 91, VEX_Tileloadd_tmm_sibmem, VEX, AMX_TILE, op0=w op1=r w=tmm2 r=rcx;rdx rm=ds:rcx;Tile
+# tileloadd tmm6,[rdx-5AA5EDCCh]
+C4E27B 4B B4 22 34125AA5, VEX_Tileloadd_tmm_sibmem, VEX, AMX_TILE, op0=w op1=r w=tmm6 r=rdx rm=ds:rdx+0xFFFFFFFFA55A1234;Tile
 # tdpbf16ps tmm2,tmm3,tmm4
 C4E25A 5C D3, VEX_Tdpbf16ps_tmm_tmm_tmm, VEX, AMX_BF16, op0=rw op1=r op2=r rw=tmm2 r=tmm3;tmm4
 # tdpbuud tmm2,tmm3,tmm4