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Remove modrm prefix

This commit is contained in:
0xd4d 2020-10-31 16:50:44 +01:00
parent e79a13c84c
commit 5f388f5545
2 changed files with 74 additions and 74 deletions
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126
src/csharp/Intel/Generator/Tables/OpCodeOperandKindDefs.txt
View File

@ -50,19 +50,19 @@ imm32, imm=32;32,
imm32sex64, imm=32;64, imm32sex64, imm=32;64,
imm64, imm=64;64, imm64, imm=64;64,
al, register=al, al, imp-reg=al,
cl, register=cl, cl, imp-reg=cl,
ax, register=ax, ax, imp-reg=ax,
dx, register=dx, dx, imp-reg=dx,
eax, register=eax, eax, imp-reg=eax,
rax, register=rax, rax, imp-reg=rax,
st0, register=st0, st0, imp-reg=st0,
es, register=es, es, imp-reg=es,
cs, register=cs, cs, imp-reg=cs,
ss, register=ss, ss, imp-reg=ss,
ds, register=ds, ds, imp-reg=ds,
fs, register=fs, fs, imp-reg=fs,
gs, register=gs, gs, imp-reg=gs,
seg_rBX_al, seg-rbx-al, seg_rBX_al, seg-rbx-al,
seg_rDI, seg-rdi, seg_rDI, seg-rdi,
@ -80,35 +80,35 @@ r32_opcode, opcode=eax,
r64_opcode, opcode=rax, r64_opcode, opcode=rax,
sti_opcode, opcode=st0, sti_opcode, opcode=st0,
bnd_reg, modrm.reg=bnd0, bnd_reg, reg=bnd0,
cr_reg, modrm.reg=cr0, lock-bit cr_reg, reg=cr0, lock-bit
dr_reg, modrm.reg=dr0, dr_reg, reg=dr0,
k_reg, modrm.reg=k0, k_reg, reg=k0,
kp1_reg, modrm.reg=k0, p1 kp1_reg, reg=k0, p1
mm_reg, modrm.reg=mm0, mm_reg, reg=mm0,
r8_reg, modrm.reg=al, r8_reg, reg=al,
r16_reg, modrm.reg=ax, r16_reg, reg=ax,
r16_reg_mem, modrm.reg=ax, mem r16_reg_mem, reg=ax, mem
r32_reg, modrm.reg=eax, r32_reg, reg=eax,
r32_reg_mem, modrm.reg=eax, mem r32_reg_mem, reg=eax, mem
r64_reg, modrm.reg=rax, r64_reg, reg=rax,
r64_reg_mem, modrm.reg=rax, mem r64_reg_mem, reg=rax, mem
seg_reg, modrm.reg=es, seg_reg, reg=es,
tmm_reg, modrm.reg=tmm0, tmm_reg, reg=tmm0,
tr_reg, modrm.reg=tr0, tr_reg, reg=tr0,
xmm_reg, modrm.reg=xmm0, xmm_reg, reg=xmm0,
ymm_reg, modrm.reg=ymm0, ymm_reg, reg=ymm0,
zmm_reg, modrm.reg=zmm0, zmm_reg, reg=zmm0,
k_rm, modrm.rm-reg-only=k0, k_rm, rm-reg=k0,
mm_rm, modrm.rm-reg-only=mm0, mm_rm, rm-reg=mm0,
r16_rm, modrm.rm-reg-only=ax, r16_rm, rm-reg=ax,
r32_rm, modrm.rm-reg-only=eax, r32_rm, rm-reg=eax,
r64_rm, modrm.rm-reg-only=rax, r64_rm, rm-reg=rax,
tmm_rm, modrm.rm-reg-only=tmm0, tmm_rm, rm-reg=tmm0,
xmm_rm, modrm.rm-reg-only=xmm0, xmm_rm, rm-reg=xmm0,
ymm_rm, modrm.rm-reg-only=ymm0, ymm_rm, rm-reg=ymm0,
zmm_rm, modrm.rm-reg-only=zmm0, zmm_rm, rm-reg=zmm0,
k_vvvv, vvvv=k0, k_vvvv, vvvv=k0,
r32_vvvv, vvvv=eax, r32_vvvv, vvvv=eax,
@ -120,29 +120,29 @@ ymm_vvvv, vvvv=ymm0,
zmm_vvvv, vvvv=zmm0, zmm_vvvv, vvvv=zmm0,
zmmp3_vvvv, vvvv=zmm0, p3 zmmp3_vvvv, vvvv=zmm0, p3
bnd_or_mem_mpx, modrm.rm=bnd0, mpx bnd_or_mem_mpx, rm=bnd0, mpx
k_or_mem, modrm.rm=k0, k_or_mem, rm=k0,
mm_or_mem, modrm.rm=mm0, mm_or_mem, rm=mm0,
r8_or_mem, modrm.rm=al, r8_or_mem, rm=al,
r16_or_mem, modrm.rm=ax, r16_or_mem, rm=ax,
r32_or_mem, modrm.rm=eax, r32_or_mem, rm=eax,
r32_or_mem_mpx, modrm.rm=eax, mpx r32_or_mem_mpx, rm=eax, mpx
r64_or_mem, modrm.rm=rax, r64_or_mem, rm=rax,
r64_or_mem_mpx, modrm.rm=rax, mpx r64_or_mem_mpx, rm=rax, mpx
xmm_or_mem, modrm.rm=xmm0, xmm_or_mem, rm=xmm0,
ymm_or_mem, modrm.rm=ymm0, ymm_or_mem, rm=ymm0,
zmm_or_mem, modrm.rm=zmm0, zmm_or_mem, rm=zmm0,
mem, modrm.mem, mem, rm-mem,
mem_mib, modrm.mem, mib mem_mib, rm-mem, mib
mem_mpx, modrm.mem, mpx mem_mpx, rm-mem, mpx
sibmem, modrm.mem, sib sibmem, rm-mem, sib
mem_vsib32x, modrm.vsib=xmm0;32, mem_vsib32x, vsib=xmm0;32,
mem_vsib32y, modrm.vsib=ymm0;32, mem_vsib32y, vsib=ymm0;32,
mem_vsib32z, modrm.vsib=zmm0;32, mem_vsib32z, vsib=zmm0;32,
mem_vsib64x, modrm.vsib=xmm0;64, mem_vsib64x, vsib=xmm0;64,
mem_vsib64y, modrm.vsib=ymm0;64, mem_vsib64y, vsib=ymm0;64,
mem_vsib64z, modrm.vsib=zmm0;64, mem_vsib64z, vsib=zmm0;64,
mem_offs, moffs, mem_offs, moffs,

22
src/csharp/Intel/Generator/Tables/OpCodeOperandKindDefsReader.cs
View File

@ -53,14 +53,14 @@ namespace Generator.Tables {
{ "br-far", 1 }, { "br-far", 1 },
{ "imm8-const", 1 }, { "imm8-const", 1 },
{ "imm", 2 }, { "imm", 2 },
{ "register", 1 }, { "imp-reg", 1 },
{ "isx", 2 }, { "isx", 2 },
{ "opcode", 1 }, { "opcode", 1 },
{ "modrm.reg", 1 }, { "reg", 1 },
{ "modrm.rm-reg-only", 1 }, { "rm-reg", 1 },
{ "vvvv", 1 }, { "vvvv", 1 },
{ "modrm.rm", 1 }, { "rm", 1 },
{ "modrm.vsib", 2 }, { "vsib", 2 },
}; };
var lines = File.ReadAllLines(filename); var lines = File.ReadAllLines(filename);
@ -141,7 +141,7 @@ namespace Generator.Tables {
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.Immediate, arg1, arg2, Register.None); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.Immediate, arg1, arg2, Register.None);
break; break;
case "register": case "imp-reg":
register = (Register)toRegister[args[0]].Value; register = (Register)toRegister[args[0]].Value;
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.ImpliedRegister, 0, 0, register); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.ImpliedRegister, 0, 0, register);
break; break;
@ -181,13 +181,13 @@ namespace Generator.Tables {
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegOpCode, 0, 0, register); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegOpCode, 0, 0, register);
break; break;
case "modrm.reg": case "reg":
flags |= OpCodeOperandKindDefFlags.Modrm; flags |= OpCodeOperandKindDefFlags.Modrm;
register = (Register)toRegister[args[0]].Value; register = (Register)toRegister[args[0]].Value;
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegModrmReg, 0, 0, register); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegModrmReg, 0, 0, register);
break; break;
case "modrm.rm-reg-only": case "rm-reg":
flags |= OpCodeOperandKindDefFlags.Modrm; flags |= OpCodeOperandKindDefFlags.Modrm;
register = (Register)toRegister[args[0]].Value; register = (Register)toRegister[args[0]].Value;
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegModrmRm, 0, 0, register); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegModrmRm, 0, 0, register);
@ -198,20 +198,20 @@ namespace Generator.Tables {
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegVvvvv, 0, 0, register); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegVvvvv, 0, 0, register);
break; break;
case "modrm.rm": case "rm":
flags |= OpCodeOperandKindDefFlags.Modrm; flags |= OpCodeOperandKindDefFlags.Modrm;
flags |= OpCodeOperandKindDefFlags.Memory; flags |= OpCodeOperandKindDefFlags.Memory;
register = (Register)toRegister[args[0]].Value; register = (Register)toRegister[args[0]].Value;
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegMemModrmRm, 0, 0, register); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.RegMemModrmRm, 0, 0, register);
break; break;
case "modrm.mem": case "rm-mem":
flags |= OpCodeOperandKindDefFlags.Modrm; flags |= OpCodeOperandKindDefFlags.Modrm;
flags |= OpCodeOperandKindDefFlags.Memory; flags |= OpCodeOperandKindDefFlags.Memory;
def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.MemModrmRm, 0, 0, Register.None); def = new OpCodeOperandKindDef(enumValue, flags, OperandEncoding.MemModrmRm, 0, 0, Register.None);
break; break;
case "modrm.vsib": case "vsib":
flags |= OpCodeOperandKindDefFlags.Modrm; flags |= OpCodeOperandKindDefFlags.Modrm;
flags |= OpCodeOperandKindDefFlags.Memory; flags |= OpCodeOperandKindDefFlags.Memory;
register = (Register)toRegister[args[0]].Value; register = (Register)toRegister[args[0]].Value;