mirror of https://github.com/nmlgc/ReC98.git
211 lines
6.5 KiB
C++
211 lines
6.5 KiB
C++
/// Custom code generation for pseudoregisters
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/// ------------------------------------------
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/// Since __emit__() always inlines, we can use it implement our own code
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/// generation to bypass compiler bugs or quirks related to pseudoregisters, by
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/// directly outputting the intended machine code:
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///
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/// • Step 1: Define opcodes and R/M bytes for all needed instructions and
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/// registers
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/// • Step 2: Implement needed operations as inlined functions via __emit__(),
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/// taking all required instruction components as parameters
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/// • Step 3: Add macros that token-paste pseudoregisters onto the prefixes of
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/// the opcode byte constants. This way, we hide the pseudoregisters
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/// from the compiler, and the constants from usage code.
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///
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/// Provides workarounds for the following issues:
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///
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/// 1) Turbo C++ 4.0 generates wrong segment prefix opcodes for the _FS and _GS
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/// pseudoregisters - 0x46 (INC SI) and 0x4E (DEC SI) rather than the correct
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/// 0x64 and 0x65, respectively. These prefixes are also not supported in
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/// inline assembly, which is limited to pre-386 anyway. Compiling via
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/// assembly (`#pragma inline`) would work and generate the correct
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/// instructions, but that would incur yet another dependency on a 16-bit
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/// TASM for something honestly quite insignificant.
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/// 2) If _SI or _DI are used within a function, Turbo C++ 4.0 always generates
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/// a `PUSH SI` and `PUSH DI` instruction in the function prolog, and a
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/// `POP DI` and `POP SI` instruction in the epilog, in this order. If a
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/// function needs both these registers and a different prolog or epilog, all
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/// use of these registers must be hidden via __emit__(). These macros can
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/// help retain some readability in this case.
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///
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/// Provides access to the following instructions that are unavailable in Turbo
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/// C++ 4.0's inline assembler, for arbitrary registers:
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///
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/// • IMUL r16, r/m16, imm8
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#if defined(__TURBOC__) && defined(__MSDOS__)
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// Declared in <dos.h> in these compilers.
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void __emit__(uint8_t __byte, ...);
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#endif
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struct X86 {
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enum Prefix {
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P_DS = 0x3E,
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P_SS = 0x36,
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P_ES = 0x26,
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P_FS = 0x64,
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P_GS = 0x65,
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P_OPERAND_SIZE = 0x66,
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};
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enum Reg8 {
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R_CL = 1,
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};
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enum Reg16 {
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R_AX = 0,
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R_DX = 2,
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R_BX = 3,
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R_SI = 6,
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R_DI = 7,
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};
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enum Reg32 {
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R_EAX = 0,
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};
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enum RM {
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RM_ADDRESS_DI = 0x05,
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RM_ADDRESS_BP = 0x06,
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};
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enum OpRegMem {
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OR_RM_R_32 = 0x09, // OR r/m32, r32
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MOV_RM_R_16 = 0x89, // MOV r/m16, r16
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MOV_RM_R_32 = 0x89, // MOV r/m32, r32
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MOV_R_RM_8 = 0x8A, // MOV r8, r/m8
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MOV_R_RM_16 = 0x8B, // MOV r16, r/m16
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MOV_R_RM_32 = 0x8B, // MOV r32, r/m32
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LEA_R_M_16 = 0x8D, // LEA r16, m
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};
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enum OpRegRegMem {
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CMP_RM_R_16 = 0x3B, // CMP r/m16, r16
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IMUL_R_RM_IMM_8 = 0x6B, // IMUL r16, r/m16, imm8
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};
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// Emitters
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// --------
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static void reg_reg(OpRegRegMem op, Reg16 dst, Reg16 src, uint8_t imm = 0) {
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if(imm) {
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__emit__(op, (0xC0 + (dst * 8) + src), imm);
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} else {
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__emit__(op, (0xC0 + (dst * 8) + src));
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}
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}
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static void reg_mem(
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OpRegMem op, Prefix prefix, RM rm, Reg16 reg, uint8_t disp = 0
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) {
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if(!(
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((prefix == P_SS) && (rm == RM_ADDRESS_BP)) ||
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((prefix == P_DS) && (rm != RM_ADDRESS_BP))
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)) {
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__emit__(prefix);
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}
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if(disp || (rm == RM_ADDRESS_BP)) {
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__emit__(op, (0x40 + ((reg * 8) + rm)), disp);
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} else {
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__emit__(op, ((reg * 8) + rm));
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}
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}
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static void reg_mem(
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OpRegMem op, Prefix prefix, RM rm, Reg32 reg, uint8_t disp = 0
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) {
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__emit__(P_OPERAND_SIZE);
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reg_mem(op, prefix, rm, static_cast<Reg16>(reg), disp);
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}
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static void mov_to_reg(Prefix prefix, RM rm, Reg8 reg, uint8_t disp = 0) {
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reg_mem(MOV_R_RM_8, prefix, rm, static_cast<Reg16>(reg), disp);
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}
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static void mov_to_reg(Prefix prefix, RM rm, Reg16 reg, uint8_t disp = 0) {
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reg_mem(MOV_R_RM_16, prefix, rm, reg, disp);
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}
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static void mov_to_reg(Prefix prefix, RM rm, Reg32 reg, uint8_t disp = 0) {
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reg_mem(MOV_R_RM_32, prefix, rm, reg, disp);
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}
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static void mov_to_mem(Prefix prefix, RM rm, Reg16 reg, uint8_t disp = 0) {
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reg_mem(MOV_RM_R_16, prefix, rm, reg, disp);
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}
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static void mov_to_mem(Prefix prefix, RM rm, Reg32 reg, uint8_t disp = 0) {
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reg_mem(MOV_RM_R_32, prefix, rm, reg, disp);
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}
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// --------
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};
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// First macro layer to transform pseudoregisters into x86 constants
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// -----------------------------------------------------------------
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#define _stack_to_reg(op, dst_reg, imm) \
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X86::reg_mem(op, X86::P_SS, X86::RM_ADDRESS_BP, X86::R##dst_reg, imm);
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#define _cmp_reg_reg(dst_reg, src_reg) \
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X86::reg_reg(X86::CMP_RM_R_16, X86::R##dst_reg, X86::R##src_reg);
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#define _imul_reg_to_reg(dst_reg, src_reg, imm) \
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X86::reg_reg(X86::IMUL_R_RM_IMM_8, X86::R##dst_reg, X86::R##src_reg, imm);
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#define _lea_local_to_reg(dst_reg, src_top, src_ptr) \
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_stack_to_reg(X86::LEA_R_M_16, dst_reg, ( \
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reinterpret_cast<uint8_t __ss *>(src_ptr) - \
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reinterpret_cast<uint8_t __ss *>(src_top) \
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));
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#define _mov_param_to_reg(dst_reg, offset) \
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_stack_to_reg(X86::MOV_R_RM_16, dst_reg, offset);
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#define _mov_to_reg(dst_reg, src_sgm, src_off, src_disp) \
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X86::mov_to_reg( \
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X86::P##src_sgm, X86::RM_ADDRESS##src_off, X86::R##dst_reg, src_disp \
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);
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#define _mov_to_mem(dst_sgm, dst_off, dst_disp, src_reg) \
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X86::mov_to_mem( \
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X86::P##dst_sgm, X86::RM_ADDRESS##dst_off, X86::R##src_reg, dst_disp \
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);
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// Removing [val] from the parameter lists of the template functions below
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// perfects the inlining.
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#define poked(sgm, off, val) \
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_EAX = val; \
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X86::reg_mem( \
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X86::MOV_RM_R_32, X86::P##sgm, X86::RM_ADDRESS##off, X86::R_EAX \
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);
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#define poke_or_d(sgm, off, val) \
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_EAX = val; \
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X86::reg_mem( \
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X86::OR_RM_R_32, X86::P##sgm, X86::RM_ADDRESS##off, X86::R_EAX \
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);
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// -----------------------------------------------------------------
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// Second macro layer to allow pseudoregister renaming
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// ---------------------------------------------------
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#define cmp_reg_reg(dst_reg, src_reg) \
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_cmp_reg_reg(dst_reg, src_reg)
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#define imul_reg_to_reg(dst_reg, src_reg, imm) \
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_imul_reg_to_reg(dst_reg, src_reg, imm)
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#define lea_local_to_reg(dst_reg, src_top, src_ptr) \
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_lea_local_to_reg(dst_reg, src_top, src_ptr)
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#define mov_param_to_reg(dst_reg, src_ptr) \
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_mov_param_to_reg(dst_reg, src_ptr)
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#define mov_to_reg(dst_reg, src_sgm, src_off, src_disp) \
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_mov_to_reg(dst_reg, src_sgm, src_off, src_disp)
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#define mov_to_mem(dst_sgm, dst_off, dst_disp, src_reg) \
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_mov_to_mem(dst_sgm, dst_off, dst_disp, src_reg)
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// ---------------------------------------------------
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/// ----------------------
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